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 SanDisk CompactFlash Memory Card
Product Manual
Version 11.0 Document No. 20-10-00038 January 2006
SanDisk Corporation
Corporate Headquarters * 140 Caspian Court * Sunnyvale, CA 94089 Phone (408) 542-0500 * Fax (408) 542-0503 www.sandisk.com
www..com
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SanDisk(R) Corporation general policy does not recommend the use of its products in life support applications where in a failure or malfunction of the product may directly threaten life or injury. Per SanDisk Terms and Conditions of Sale, the user of SanDisk products in life support applications assumes all risk of such use and indemnifies SanDisk against all damages. See "Limited Warranty" and "Disclaimer of Liability." This document is for information use only and is subject to change without prior notice. SanDisk Corporation assumes no responsibility for any errors that may appear in this document, nor for incidental or consequential damages resulting from the furnishing, performance or use of this material. No part of this document may be reproduced, transmitted, transcribed, stored in a retrievable manner or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the prior written consent of an officer of SanDisk Corporation. All parts of the SanDisk documentation are protected by copyright law and all rights are reserved. SanDisk and the SanDisk logo are registered trademarks of SanDisk Corporation. CompactFlash is a U.S. registered trademark of SanDisk Corporation. Product names mentioned herein are for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. (c) 2006 SanDisk Corporation. All rights reserved. SanDisk products are covered or licensed under one or more of the following U.S. Patent Nos. 5,070,032; 5,095,344; 5,168,465; 5,172,338; 5,198,380; 5,200,959; 5,268,318; 5,268,870; 5,272,669; 5,418,752; 5,602,987. Other U.S. and foreign patents awarded and pending. Lit. No. 20-10-00038 Rev. 11.0BA 01/2006 Printed in U.S.A.
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CompactFlash Memory Card Product Manual, Rev. 11.0 (c)2006 SanDisk Corporation
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Revision History * Revisions before Rev. 5--initial release and general changes. * Revision 5--general editorial changes, CF Type II information added, new higher capacities products added, some lower capacities removed, new card reader/writer vendor added. * Revision 6--added new 256 Mbit technology products, general and editorial changes. * Revision 7--changes to Translate Sector command (page 73) and Device Control Register Enable bit (page 53) * Revision 8--removed CF Type II information, added new higher capacity products, removed some lower capacity products, broadened temperature ranges for 3.3V and 5V operation, modified read & write timing specifications. * Revision 9--manual format and minor technical and editorial changes. * Revision 9.1--minor technical and editorial changes. * Revision 10.0--technical and editorial changes * Revision 10.1--technical and editorial changes * * * * * * Revision 10.2--revisions in power requirements and general text edits Revision 10.3--revisions in power requirements Revision 10.4--revisions in table 5-8 and table 6-1 Revision 10.5--revisions to Section 2.2, 2.6, and Appendix A Revision 10.6--updated part numbers Revision 10.7--updated to include DMA mode if supported; revised I/O write timing diagram & pwrup/dwn & other minor editorial changes; updated App C * Revision 10.8--updated part numbers; appendices; Table 5-8; feature bullet * Revision 10.9--updated values * Revision 11.0--updated capacity model; Identify Device Table; minor edits; added MB/GB calculation footnotes
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Table of Contents
1. Introduction to the CompactFlash Memory Card ............................................................................................... 1-1 1.1. Scope ................................................................................................................................................. 1-1 1.2. System Features................................................................................................................................. 1-2 1.3. PCMCIA Standard ............................................................................................................................ 1-2 1.4. CompactFlash Specification.............................................................................................................. 1-3 1.5. Related Documentation ..................................................................................................................... 1-3 1.6. Functional Description ...................................................................................................................... 1-3 1.6.1. Technology Independence....................................................................................................... 1-4 1.6.2. Defect and Error Management ................................................................................................ 1-4 1.6.3. Wear Leveling......................................................................................................................... 1-4 1.6.4. Using the Erase Sector and Write without Erase Commands.................................................. 1-4 1.6.5. Automatic Sleep Mode............................................................................................................ 1-5 1.6.6. Dynamic Adjustment of Performance versus Power Consumption ........................................ 1-5 1.6.7. Power Supply Requirements ................................................................................................... 1-5 2. Product Specifications ........................................................................................................................................ 2-1 2.1. System Environmental Specifications ............................................................................................... 2-1 2.2. System Power Requirements............................................................................................................. 2-1 2.3. System Performance.......................................................................................................................... 2-2 2.4. System Reliability ............................................................................................................................. 2-2 2.5. Physical Specifications...................................................................................................................... 2-2 2.6. Capacity Specifications ..................................................................................................................... 2-3 3. CompactFlash Memory Card Interface Description ........................................................................................... 3-1 3.1. Physical Description.......................................................................................................................... 3-1 3.1.1. Pin Assignments and Pin Type................................................................................................ 3-1 3.2. Electrical Description ........................................................................................................................ 3-3 3.3. Electrical Specification...................................................................................................................... 3-6 3.3.1. Input Leakage Control............................................................................................................. 3-7 3.3.2. Input Characteristics................................................................................................................ 3-7 3.3.3. Output Drive Type .................................................................................................................. 3-7 3.3.4. Output Drive Characteristics ................................................................................................... 3-8 3.3.5. Power-up/Power-down Timing ............................................................................................... 3-8 3.3.6. Common Memory Read Timing ............................................................................................. 3-10 3.3.7. Common and Attribute Memory Write Timing ...................................................................... 3-11 3.3.8. Attribute Memory Read Timing Specification........................................................................ 3-12 3.3.9. Memory Timing Diagrams...................................................................................................... 3-12 3.3.10. I/O Read (Input) Timing Specification.................................................................................. 3-14 3.3.11. I/O Write (Output) Timing Specification .............................................................................. 3-16 3.3.12. True IDE Mode ..................................................................................................................... 3-17 3.3.12.1. Deskewing............................................................................................................ 3-17 3.3.12.2. Transfer Timing ................................................................................................... 3-17 3.4. Card Configuration............................................................................................................................ 3-20 3.4.1. Attribute Memory Function..................................................................................................... 3-21 3.4.2. Configuration Option Register (Address 200h in Attribute Memory) .................................... 3-22 3.4.3. Card Configuration and Status Register (Address 202h in Attribute Memory) ...................... 3-23 3.4.4. Pin Replacement Register (Address 204h in Attribute Memory)............................................ 3-23 3.4.5. Socket and Copy Register (Address 206h in Attribute Memory ............................................. 3-24 3.5. I/O Transfer Function........................................................................................................................ 3-24 3.5.1. I/O Function ............................................................................................................................ 3-25
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3.6. Common Memory Transfer Function................................................................................................ 3-25 3.6.1. Common Memory Function .................................................................................................... 3-25 3.7. True IDE Mode I/O Transfer Function.............................................................................................. 3-26 3.7.1. True IDE Mode I/O Function.................................................................................................. 3-26 4. ATA Drive Register Set Definition and Protocol ............................................................................................... 4-1 4.1. I/O Primary and Secondary Address Configurations ........................................................................ 4-1 4.2. Contiguous I/O Mapped Addressing ................................................................................................. 4-2 4.3. Memory Mapped Addressing ............................................................................................................ 4-3 4.4. True IDE Mode Addressing .............................................................................................................. 4-4 4.5. ATA Registers................................................................................................................................... 4-4 4.5.1. Data Register (Address--1F0[170];Offset 0, 8, 9).................................................................. 4-4 4.5.2. Error Register (Address--1F1[171]; Offset 1, 0Dh Read Only)............................................. 4-5 4.5.3. Feature Register (Address--1F1[171]; Offset 1, 0Dh Write Only.......................................... 4-5 4.5.4. Sector Count Register (Address--1F2[172]; Offset 2) ........................................................... 4-5 4.5.5. Sector Number (LBA 7-0) Register (Address--1F3[173]; Offset 3) ...................................... 4-5 4.5.6. Cylinder Low (LBA 15-8) Register (Address--1F4[174]; Offset 4) ...................................... 4-6 4.5.7. Cylinder High (LBA 23-16) Register (Address--1F5[175]; Offset 5) ................................... 4-6 4.5.8. Drive/Head (LBA 27-24) Register (Address 1F6[176]; Offset 6)........................................... 4-6 4.5.9. Status & Alternate Status Registers (Address 1F7[177]&3F6[376]; Offsets 7 & Eh) ............ 4-6 4.5.10. Device Control Register (Address--3F6[376]; Offset Eh) ................................................... 4-7 4.5.11. Card (Drive) Address Register (Address 3F7[377]; Offset Fh) ............................................ 4-7 5. ATA Command Description............................................................................................................................... 5-1 5.1. ATA Command Set ........................................................................................................................... 5-1 5.1.1. Check Power Mode--98H, E5H ............................................................................................. 5-2 5.1.2. Execute Drive Diagnostic--90H............................................................................................. 5-3 5.1.3. Erase Sector(s)--C0H ............................................................................................................. 5-3 5.1.4. Format Track--50H ................................................................................................................ 5-4 5.1.5. Identify Drive--ECH .............................................................................................................. 5-4 5.1.5.1. Word 0: General Configuration ............................................................................ 5-6 5.1.5.2. Word 1: Default Number of Cylinders.................................................................. 5-6 5.1.5.3. Word 3: Default Number of Heads ....................................................................... 5-6 5.1.5.4. Word 4: Number of Unformatted Bytes per Track ............................................... 5-6 5.1.5.5. Word 5: Number of Unformatted Bytes per Sector .............................................. 5-7 5.1.5.6. Word 6: Default Number of Sectors per Track ..................................................... 5-7 5.1.5.7. Words 7-8: Number of Sectors per Card............................................................... 5-7 5.1.5.8. Words 10-19: Memory Card Serial Number......................................................... 5-7 5.1.5.9. Word 20: Buffer Type........................................................................................... 5-7 5.1.5.10. Word 21: Buffer Size .......................................................................................... 5-7 5.1.5.11. Word 22: ECC Count.......................................................................................... 5-7 5.1.5.12. Words 23-26: Firmware Revision....................................................................... 5-7 5.1.5.13. Words 27-46: Model Number ............................................................................. 5-7 5.1.5.14. Word 47: Read/Write Multiple Sector Count...................................................... 5-8 5.1.5.15. Word 48: Double Word Support ......................................................................... 5-8 5.1.5.16. Word 49: Capabilities ......................................................................................... 5-8 5.1.5.17. Word 51: PIO Data Transfer Cycle Timing Mode.............................................. 5-8 5.1.5.18. Word 52: Single Word DMA Data Transfer Cycle Timing Mode...................... 5-8 5.1.5.19. Word 53: Translation Parameters Valid.............................................................. 5-8 5.1.5.20. Words 54-56: Current Number of Cylinders, Heads, Sectors/Track................... 5-8 5.1.5.21. Words 57- 58: Current Capacity ......................................................................... 5-8 5.1.5.22. Word 59: Multiple Sector Setting ....................................................................... 5-8 5.1.5.23. Words 60-61: Total Sectors Addressable in LBA Mode..................................... 5-9 5.1.5.24. Word 64: Advanced PIO Transfer Modes Supported ......................................... 5-9 5.1.5.25. Word 67: Minimum PIO Transfer Cycle Time Without Flow Control............... 5-9
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Table of Contents
5.1.5.26. Word 68: Minimum PIO Transfer Cycle Time With Flow Control.................... 5-9 5.1.6. Idle--97H, E3H ...................................................................................................................... 5-11 5.1.7. Idle Immediate--95H, E1H .................................................................................................... 5-12 5.1.8. Initialize Drive Parameters--91H ........................................................................................... 5-12 5.1.9. Read Buffer--E4H.................................................................................................................. 5-13 5.1.10. Read Multiple--C4H ............................................................................................................ 5-13 5.1.11. Read Long Sector--22H, 23H .............................................................................................. 5-14 5.1.12. Read Sector(s)--20H, 21H.................................................................................................... 5-15 5.1.13. Read Verify Sector(s)--40H, 41H ........................................................................................ 5-15 5.1.14. Recalibrate--1XH................................................................................................................. 5-16 5.1.15. Request Sense--03H............................................................................................................. 5-16 5.1.16. Seek--7XH ........................................................................................................................... 5-17 5.1.17. Set Features--EFH................................................................................................................ 5-18 5.1.18. Set Multiple Mode--C6H ..................................................................................................... 5-19 5.1.19. Set Sleep Mode- 99H, E6H ................................................................................................... 5-19 5.1.20. Standby--96H, E2H.............................................................................................................. 5-20 5.1.21. Standby Immediate--94H, E0H............................................................................................ 5-20 5.1.22. Translate Sector--87H.......................................................................................................... 5-21 5.1.23. Wear Level--F5H ................................................................................................................. 5-21 5.1.24. Write Buffer--E8H ............................................................................................................... 5-22 5.1.25. Write Long Sector--32H, 33H ............................................................................................. 5-22 5.1.26. Write Multiple Command--C5H.......................................................................................... 5-23 5.1.27. Write Multiple without Erase--CDH.................................................................................... 5-24 5.1.28. Write Sector(s)--30H, 31H................................................................................................... 5-24 5.1.29. Write Sector(s) without Erase--38H..................................................................................... 5-25 5.1.30. Write Verify Sector(s)--3CH ............................................................................................... 5-25 5.2. Error Posting ..................................................................................................................................... 5-26 6. CIS Description .................................................................................................................................................. 6-1 Appendix A. Ordering Information ........................................................................................................................ A-1 Appendix B. Technical Support Services ............................................................................................................... B-1 Appendix C. SanDisk Worldwide Sales Offices .................................................................................................... C-1 Appendix D. Limited Warranty .............................................................................................................................. D-1 Appendix E. Disclaimer of Liability....................................................................................................................... E-1
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1. Introduction to the CompactFlash Memory Card
The SanDisk CompactFlash(R) Memory Card (CF) products provide high capacity solid-state flash memory that electrically complies with the Personal Computer Memory Card International Association ATA (PC Card ATA) standard. (In Japan, the applicable standards group is JEIDA.) The CompactFlash Memory Card Series also supports a True IDE Mode that is electrically compatible with an IDE disk drive. The original CF form factor card can be used in any system that has a CF slot, and with a Type II PCMCIA adapter can be used in any system that has a PCMCIA Type II or Type III socket. The CompactFlash Memory Cards use SanDisk Flash memory, which was designed by SanDisk specifically for use in mass storage applications. In addition to the mass storage specific Flash memory chips, the CompactFlash Memory Cards include an on-card intelligent controller that provides a high level interface to the host computer. This interface allows a host computer to issue commands to the memory card to read or write blocks of memory. The host addresses the card in 512 byte sectors. Each sector is protected by a powerful Error Correcting Code (ECC). The CompactFlash Memory Card on-card intelligent controller manages interface protocols, data storage and retrieval as well as ECC, defect handling and diagnostics, power management and clock control. Once the CompactFlash Memory Card has been configured by the host, it appears to the host as a standard ATA (IDE) disk drive. Additional ATA commands have been provided to enhance system performance. The host system can support as many cards as there are CompactFlash and PCMCIA Type II or III card slots. The original form factor CompactFlash Memory Cards require a PCMCIA Type II Adapter to be used in a PCMCIA Type II or Type III socket. Figure 1-1 shows a block diagram of the CompactFlash Memory Card.
Data In/O ut
Host Interface
SanDisk Single Chip Controller
Control
SanDisk Flash Modules
SanDisk CompactFlash
Figure 1-1. CompactFlash Memory Card Block Diagram
1.1. Scope
This document describes the key features and specifications of CompactFlash Memory Cards, as well as the information required to interface this product to a host system. Retail CompactFlash specifications are not covered in this manual.
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Introduction to the CompactFlash Memory Card
1.2. System Features
CompactFlash provides the following system features:
* * * * * * * * * * * * * * *
Up to 16 GB of mass storage data PC Card ATA protocol compatible True IDE Mode compatible Very low CMOS power Very high performance Very rugged Low weight Noiseless Low Profile +5 Volts or +3.3 Volts operation Automatic error correction and retry capabilities Supports power down commands and sleep modes Non-volatile storage (no battery required) MTBF >1,000,000 hours Minimum 10,000 insertions
1.3. CompactFlash Specification
CompactFlash Memory Cards are fully compatible with the CompactFlash Specification published by the CompactFlash Association. Contact the CompactFlash Association for more information. CompactFlash Association P.O. Box 51537 Palo Alto, CA 94303 USA Phone: 415-843-1220 FAX: 415-493-1871 www.compactflash.org
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Introduction to the CompactFlash Memory Card
1.4. PCMCIA Standard
CompactFlash Memory Cards are fully electrically compatible with the PCMCIA specifications listed below:
* *
PCMCIA PC Card Standard, 7.0, February 1999 PCMCIA PC Card ATA Specification, 7.0, February 1999
These specifications may be obtained from: PCMCIA 2635 North First St., Ste. 209 San Jose, CA 95131 USA Phone: 408-433-2273 FAX: 408-433-9558
1.5. Related Documentation
ATA operation is governed by the ATA-4 specification published by ANSI. You may wish to consult the following document: American National Standard X3.221: AT Attachment for Interface for Disk Drives Document Documentation can be ordered from Global Engineering Documents by calling: 1-800-854-7179
1.6. Functional Description
CompactFlash Memory Cards contain a high level, intelligent subsystem as shown in the block diagram, Figure 1-1. This intelligent (microprocessor) subsystem provides many capabilities not found in other types of memory cards. These capabilities include the following:
* * * * *
Standard ATA register and command set (same as found on most magnetic disk drives). Host independence from details of erasing and programming flash memory. Sophisticated system for managing defects (analogous to systems found in magnetic disk drives). Sophisticated system for error recovery including a powerful error correction code (ECC). Power management for low power operation.
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Introduction to the CompactFlash Memory Card
1.6.1. Technology Independence The 512-byte sector size of the CompactFlash Memory Card is the same as that in an IDE magnetic disk drive. To write or read a sector (or multiple sectors), the host computer software simply issues a Read or Write command to the CompactFlash Memory Card. This command contains the address and the number of sectors to write/read. The host software then waits for the command to complete. The host software does not get involved in the details of how the flash memory is erased, programmed or read. This is extremely important as flash devices are expected to get more and more complex in the future. Since the CompactFlash Memory Card Series uses an intelligent on-board controller, the host system software will not require changing as new flash memory evolves. In other words, systems that support the CompactFlash Memory Card today will be able to access future SanDisk cards built with new flash technology without having to update or change host software. 1.6.2. Defect and Error Management CompactFlash Memory Cards contain a sophisticated defect and error management system. This system is analogous to the systems found in magnetic disk drives and in many cases offers enhancements. If necessary, CompactFlash Memory Cards will rewrite data from a defective sector to a good sector. This is completely transparent to the host and does not consume any user data space. The CompactFlash Memory Card soft error rate specification is much better than the magnetic disk drive specification. In the extremely rare case a read error does occur, CompactFlash Memory Cards have innovative algorithms to recover the data. These defect and error management systems, coupled with the solid state construction, give CompactFlash Memory Cards unparalleled reliability. 1.6.3. Wear Leveling Wear Leveling is an intrinsic part of the Erase Pooling functionality of SanDisk CF using NAND memory. The CF WEAR LEVEL command is supported as a NOP operation to maintain backward compatibility with existing software utilities. 1.6.4. Using the Erase Sector and Write without Erase Commands CompactFlash Memory Cards support the CF ERASE SECTOR and WRITE WITHOUT ERASE commands. In some applications, write operations may be faster if the addresses being written are first erased with the ERASE SECTOR command. WRITE WITHOUT ERASE behaves as a normal write command and no performance gain results from its use.
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Introduction to the CompactFlash Memory Card
1.6.5. Automatic Sleep Mode A unique feature of the SanDisk CompactFlash Memory Card (and other SanDisk products) is automatic entrance and exit from sleep mode. Upon completion of a command, the CompactFlash Card will enter sleep mode to conserve power if no further commands are received within 5 msec. The host does not have to take any action for this to occur. In most systems, the CompactFlash Memory Card is in sleep mode except when the host is accessing it, thus conserving power. Note that the delay from command completion to entering sleep mode can be adjusted. When the host is ready to access the CompactFlash Memory Card and it is in sleep mode, any command issued to the CompactFlash Card will cause it to exit sleep and respond. The host does not have to follow the ATA protocol of issuing a reset first. It may do this if desired, but it is not needed. By not issuing the reset, performance is improved through the reduction of overhead but this must be done only for the SanDisk products as other ATA products may not support this feature. 1.6.6. Dynamic Adjustment of Performance versus Power Consumption This feature is no longer supported. This command will be treated as a NOP (No Operation) to guarantee backward compatibility. 1.6.7. Power Supply Requirements This is a dual voltage product, which means it will operate at a voltage range of 3.30 volts 5% or 5.00 volts 10%. Per the PCMCIA specification Section 2.1.1, the host system must apply 0 volts in order to change a voltage range. This same procedure of providing 0 volts to the card is required if the host system applies an input voltage outside the desired voltage by more than 15%. This means less than 4.25 volts for the 5.00-volt range and less than 2.75 volts for the 3.30 volt range.
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Introduction to the CompactFlash Memory Card
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2. Product Specifications
For all the following specifications, values are defined at ambient temperature and nominal supply voltage unless otherwise stated.
2.1. System Environmental Specifications
Table 2-1. Environmental Specifications
Temperature Humidity Acoustic Noise Vibration Shock Altitude (relative to sea level) Operating: 0 C to 70 C Non-Operating: -25 C to 85 C Operating: 8% to 95%, non-condensing Non-Operating: 8% to 95%, non-condensing 0 dB Operating: 15 G peak to peak maximum Non-Operating: 15 G peak to peak max Operating: 2,000 G maximum Non-Operating: 2,000 G maximum Operating: 80,000 feet maximum Non-Operating: 80,000 feet maximum
2.2. System Power Requirements
Table 2-2. Power Requirements
DC Input Voltage (VCC) 100 mV max. ripple (p-p) Memory Subsystem
1
3.3 V 5%
5 V 10%
Sleep
Up to 512 MB 1.0 GB Over 1.0 GB
300 600 1 mA 50 mA 65 mA 100 mA
500 800 1.2 mA 55 mA 70 mA 100 mA
Read Write Read/Write Peak
NOTES: All values quoted are typical at 25 C and nominal supply voltage unless otherwise stated. Sleep mode currently is specified under the condition that all card inputs are static CMOS levels and in a "Not Busy" operating state.
1
Maximum average value.
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Product Specifications
2.3. System Performance
All performance timings assume the CompactFlash Memory Card Series controller is in the default (i.e., fastest) mode. Table 2-3. Performance
Start Up Times Sleep to write: 2.5 ms maximum Sleep to read: 20 ms maximum Reset to ready: 50 ms typical 400 ms maximum Programmable 20.0 MB/sec burst 16.0 MB/sec burst Command to DRQ 50 ms maximum
Active to Sleep Delay Data Transfer Rate To/From Flash Data Transfer Rate To/From Host Controller Overhead
NOTE: The Sleep to Write and Sleep to Read times are the times it takes the CompactFlash Memory Card to exit sleep mode when any command is issued by the host to when the card is reading or writing. CompactFlash Memory Cards do not require a reset to exit sleep mode (see Section 1.7.5).
2.4. System Reliability
Table 2-4. Reliability
MTBF (@ 25C) Preventive Maintenance Data Reliability >1,000,000 hours None <1 non-recoverable error in 1014 bits read <1 erroneous correction in 1020 bits read
2.5. Physical Specifications
Refer to Table 2-5 and see Figure 2-1 for CompactFlash Memory Card physical specifications and dimensions. Table 2-5. Physical Specifications
CompactFlash Weight: 11.4 g (.40 oz) typical, 14.2 g (.50 oz) maximum Length: 36.40 0.15 mm (1.433 .006 in) Width: 42.80 0.10 mm (1.685 .004 in) Thickness: 3.3 mm 0.10 mm (.130 .004 in) (Excluding Lip)
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Product Specifications
.063.002 [1.60] .130.004 [3.30]
26 1 .040.003 [1.00]
50 25 .040.003 [1.00] .039.002 [1.00]
2X .472.004
[12.00]
2X 1.015.003 [25.78]
1.433.006
.030.003 [0.8]
1.640.005 [41.66] 4X R.020.004 [0.5] 1.685.004 [42.80]
.025.003 [0.6]
Figure 2-1. CompactFlash Memory Card Dimensions Table 2-6 lists the CompactFlash Memory Card PC Card Adapter physical specifications and Figure 2-2 shows CompactFlash Memory Card PC Card Adapter dimensions. Table 2-6 Adapter Physical Specifications
CF Adapter Weight Length Width Thickness 33 g (1.16 oz) typical 85.6 0.20 mm (3.370 .008 in) 54.0 0.10 mm (2.126 .004 in) 5.0 mm Max (0.1968 in)
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2X .118.003 [3.00]
[36.40]
OP T
.096.003 [2.4]
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Product Specifications
0.196 [5.0]
0.130 [3.3]
2.126 [54.0]
3.370 [85.6]
1.196 [30.4]
.866 [22.0]
1.536 [39.03] .472 [12.0] .078 [2.0] 1.694 [43.03]
0.138 [3.5]
Figure 2-2 CompactFlash Memory Card Adapter Dimensions
2.6. Capacity Specifications
Table 2-7 shows the specific capacity for the various models and the default number of heads, sectors/track and cylinders. Table 2-7. Model Capacities
Model No. Capacity2 Capacity (formatted in bytes) 32,112,640 64,225,280 128,450,560 256,901,120 Sectors/Card (Max LBA+1) 62,720 125,440 250,880 501,760 No. of Heads 4 8 8 16 No. of Sectors/Track 32 32 32 32 No. of Cylinders 490 490 980 980
SDCFJ-32-388 SDCFJ-64-388 SDCFJ-128-388 SDCFJ-256-388
2
32 MB 64 MB 128 MB 256 MB
1 megabyte (MB)= 1 million bytes; 1 gigabyte (GB)= 1 billion bytes. Some of the listed capacity is used for formatting and other functions, and thus is not available for data storage.
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Product Specifications
Model No.
Capacity2
Capacity (formatted in bytes) 512,483,328 1,024,966,656 2,048,901,120 4,097,802,240 512,483,328 1,024,966,656 2,048,901,120 4,097,802,240 4,098,834,432 8,195,604,480 12,293,406,720 16,391,208,960
Sectors/Card (Max LBA+1) 1,000,944 2,001,888 4,001,760 8,003,520 1,000,944 2,001,888 4,001,760 8,003,520 8,005,536 16,007,040 24,010,560 32,014,080
No. of Heads 16 16 16 16 16 16 16 16 16 16 16 16
No. of Sectors/Track 63 63 63 63 63 63 63 63 63 63 63 63
No. of Cylinders 993 1,986 3,970 7,940 993 1,986 3,970 7,940 7,942 15,880 23,820 31,760
SDCFJ-512-388 SDCFJ-1024-388 SDCFJ-2048-388 SDCFJ-4096-388 SDCFH-512-388 SDCFH-1024-388 SDCFH-2048-388 SDCFH-4096-388 SDCFH-4096-3883 SDCFH-8192-388 SDCFH-12288-388 SDCFH-16384-388
512 MB 1024 MB 2048 MB 4096 MB 512 MB 1024 MB 2048 MB 4096 MB 4096 MB 8192 MB 12,288 MB 16,384 MB
3
4-GB with switch.
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Product Specifications
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3. CompactFlash Memory Card Interface Description
3.1. Physical Description
The host is connected to the CompactFlash Memory Card using a standard 50-pin connector consisting of two rows of 25 female contacts each on 50 mil (1.27 mm) centers. 3.1.1. Pin Assignments and Pin Type The signal/pin assignments are listed in Table 3-1. Low active signals have a "-" prefix. Pin types are Input, Output or Input/Output. Sections 3.3.1 to 3.3.4 define the DC characteristics for all input and output type structures. Table 3-1. Pin Assignments and Pin Type
PC Card Memory Mode Pin Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Signal Name GND D03 D04 D05 D06 D07 -CE1 A10 -OE A09 A08 A07 VCC A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 WP I I I I I I I I/O I/O I/O O I/O I/O I/O I/O I/O I I I I I I Pin Type In, Out4 Type Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U I1Z I3U I1Z I1Z I1Z Power I1Z I1Z I1Z I1Z I1Z I1Z I1Z I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 OT3 Pin Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PC Card I/O Mode Signal Name GND D03 D04 D05 D06 D07 -CE1 A10 -OE A09 A08 A07 VCC A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 -IOIS16 I I I I I I I I/O I/O I/O O I/O I/O I/O I/O I/O I I I I I I Pin Type In, Out4 Type Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U I1Z I3U I1Z I1Z I1Z Power I1Z I1Z I1Z I1Z I1Z I1Z I1Z I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 OT3 Pin Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 True IDE Mode Signal Name GND D03 D04 D05 D06 D07 -CS0 A102 -ATA SEL A092 A082 A072 VCC A062 A052 A042 A032 A02 A01 A00 D00 D01 D02 -IOCS16 I I I I I I I I/O I/O I/O O I/O I/O I/O I/O I/O I I I I I I Pin Type In, Out4 Type Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3Z I1Z I3U I1Z I1Z I1Z Power I1Z I1Z I1Z I1Z I1Z I1Z I1Z I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 ON3
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CompactFlash Memory Card Interface Description
PC Card Memory Mode Pin Num 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name -CD2 -CD1 D111 D121 D131 D141 D151 -CE21 -VS1 -IORD -IOWR -WE RDY/BSY VCC -CSEL5 -VS2 RESET -WAIT -INPACK -REG BVD2 BVD1 D081 D091 D101 GND I O I O O I I/O I/O I/O I/O I/O Pin Type O O I/O I/O I/O I/O I/O I O I I I O In, Out4 Type Ground Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U Ground I3U I3U I3U OT1 Power I2Z OPEN I2Z OT1 OT1 I3U I1U,OT1 I1U,OT1 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 Ground Pin Num 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PC Card I/O Mode Signal Name -CD2 -CD1 D111 D121 D131 D141 D151 -CE21 -VS1 -IORD -IOWR -WE IREQ VCC -CSEL5 -VS2 RESET -WAIT -INPACK -REG -SPKR -STSCHG D081 D091 D101 GND I O I O O I I/O I/O I/O I/O I/O Pin Type O O I/O I/O I/O I/O I/O I O I I I O In, Out4 Type Ground Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U Ground I3U I3U I3U OT1 Power I2Z OPEN I2Z OT1 OT1 I3U I1U,OT1 I1U,OT1 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 Ground Pin Num 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
True IDE Mode Signal Name -CD2 -CD1 D111 D121 D131 D141 D151 -CS11 -VS1 -IORD -IOWR -WE3 INTRQ VCC -CSEL -VS2 -RESET IORDY -DMARQ -DMACK6 -DASP -PDIAG D081 D091 D101 GND I O I O O I I/O I/O I/O I/O I/O Pin Type O O I/O I/O I/O I/O I/O I O I I I O In, Out4 Type Ground Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3Z Ground I3Z I3Z I3U OZ1 Power I2U OPEN I2Z ON1 OZ1 I3U I1U,ON1 I1U,ON1 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 Ground
NOTE: 1. These signals are required only for 16-bit access and not required when installed in 8-bit systems. For lowest power dissipation, leave these signals open. 2. Should be grounded by the host. 3. Should be tied to VCC by the host. 4. Please refer to Section 3.3 for definitions of In, Out type. 5. The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled up in the card in these modes, it should not be left floating by the host in PC Card modes. In these modes, the pin should be connected by the host to PC Card A25 or grounded by the host. 6. If DMA operations are not used, the signal should be held high or tied to VCC by the host. For proper operation in older hosts: while DMA operations are not active, the card shall ignore this signal, including a floating condition.
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CompactFlash Memory Card Interface Description
3.2. Electrical Description
The CompactFlash Memory Card Series is optimized for operation with hosts, which support the PCMCIA I/O interface standard conforming to the PC Card ATA specification. However, the CompactFlash Card may also be configured to operate in systems that support only the memory interface standard. The configuration of the CompactFlash Card will be controlled using the standard PCMCIA configuration registers starting at address 200h in the Attribute Memory space of the CompactFlash Memory Card. Table 3-2 describes the I/O signals. Signals whose source is the host are designated as inputs while signals that the CompactFlash Memory Card sources are outputs. The CompactFlash Card logic levels conform to those specified in the PCMCIA Release 2.1 Specification. See Section 3.3 for definitions of Input and Output type. Table 3-2. Signal Description
Signal Name A10--A0 (PC Card Memory Mode) Dir. I Pin Description
8, 10, 11, 12, 14, These address lines along with the -REG signal are used to select the following: The I/O port address registers within the CompactFlash Card, the memory mapped port 15, 16, 17, 18, address registers within the card, a byte in the card's information structure and its 19, 20 configuration control and status registers. This signal is the same as the PC Card Memory Mode signal.
A10--A0 (PC Card I/O Mode) A2--A0 (True IDE Mode) A10--A3 (True IDE Mode) BVD1 (PC Card Memory Mode) -STSCHG (PC Card I/O Mode) Status Changed -PDIAG (True IDE Mode) BVD2 (PC Card Memory Mode) -SPKR (PC Card I/O Mode) -DASP (True IDE Mode) -CD1, -CD2 (PC Card Memory Mode) -CD1, -CD2 (PC Card I/O Mode) -CD1, -CD2 (True IDE Mode) O 26, 25 I/O 45 I 18, 19, 20
In True IDE Mode only A[2:0] is used to select the one of eight registers in the Task File. In True IDE Mode these remaining address lines should be grounded by the host.
I/O
46
This signal is asserted high as the BVD1 signal since a battery is not used with this product. This signal is asserted low to alert the host to changes in the RDY/-BSY and Write Protect states, while the I/O interface is configured. Its use is controlled by the Card Config and Status Register. In the True IDE Mode, this input/output is the Pass Diagnostic signal in the Master/Slave handshake protocol. This output line is always driven to a high state in Memory Mode since a battery is not required for this product. This output line is always driven to a high state in I/O Mode since this product does not support the audio function. In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in the Master/Slave handshake protocol. These Card Detect pins are connected to ground on the CompactFlash Card. They are used by the host to determine if the card is fully inserted into its socket. This signal is the same for all modes. This signal is the same for all modes.
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CompactFlash Memory Card Interface Description
Signal Name -CE1, -CE2 (PC Card Memory Mode) Card Enable
Dir. I
Pin 7, 32
Description These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. -CE2 always accesses the odd byte of the word. -CE1 accesses the even byte or the Odd byte of the word depending on A0 and -CE2. A multiplexing scheme based on A0, -CE1, -CE2 allows 8 bit hosts to access all data on D0-D7. See Tables 3-11, 3-12, 3-15, and 3-16. This signal is the same as the PC Card Memory Mode signal.
-CE1, -CE2 (PC Card I/O Mode) Card Enable -CS0, -CS1 (True IDE Mode) -CSEL (PC Card Memory Mode) -CSEL (PC Card I/O Mode) -CSEL (True IDE Mode) D15--D00 (PC Card Memory Mode) I/O 31, 30, 29, 28, 27, 49, 48, 47, 6, 5, 4, 3, 2, 23, 22, 21 I 39
In the True IDE Mode -CS0 is the chip select for the task file registers while -CS1 is used to select the Alternate Status Register and the Device Control Register. This signal is not used for this mode. This signal is not used for this mode. This internally pulled up signal is used to configure this device as a Master or a Slave when configured in the True IDE Mode. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. These lines carry the Data, Commands and Status information between the host and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB of the Odd Byte of the Word. These signals are the same as the PC Card Memory Mode signal. In True IDE Mode all Task File operations occur in byte mode on the low order bus D00-D07 while all data transfers are 16 bits using D00-D15. -1, 50 Ground. This signal is the same for all modes. This signal is the same for all modes. O 43 This signal is not used in this mode. The Input Acknowledge signal is asserted by the CompactFlash Card when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the card and the CPU. This signal is used for DMA data transfers between host and device and is asserted by the device when it is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR- and DIOW-. This signal is used in a handshake manner with DMACK- (i.e., the device waits until the host asserts DMACK- before negating DMARQ, and reasserting DMARQ if there is more data to transfer). I 34 This signal is not used in this mode. This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the CompactFlash Card when the card is configured to use the I/O interface. In True IDE Mode, this signal has the same function as in PC Card I/O Mode.
D15--D00 (PC Card I/O Mode) D15--D00 (True IDE Mode) GND (PC Card Memory Mode) GND (PC Card I/O Mode) GND (True IDE Mode) -INPACK ( PC Card Memory Mode) -INPACK ( PC Card I/O Mode) Input Acknowledge -DMARQ (True IDE Mode)
-IORD (PC Card Memory Mode) -IORD (PC Card I/O Mode) -IORD (True IDE Mode)
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Signal Name -IOWR (PC Card Memory Mode) -IOWR (PC Card I/O Mode)
Dir. I
Pin 35 This signal is not used in this mode.
Description
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the CompactFlash controller registers when the card is configured to use the I/O interface. The clocking will occur on the negative to positive edge of the signal (trailing edge).
-IOWR (True IDE Mode) -OE (PC Card Memory Mode) -OE (PC Card I/O Mode) -ATA SEL (True IDE Mode) RDY/-BSY (PC Card Memory Mode) O 37 I 9
In True IDE Mode, this signal has the same function as in PC Card I/O Mode. This is an Output Enable strobe generated by the host interface. It is used to read data from the CompactFlash Card in Memory Mode and to read the CIS and configuration registers. In PC Card I/O Mode, this signal is used to read the CIS and configuration registers. To enable True IDE Mode this input should be grounded by the host. In Memory Mode this signal is set high when the CompactFlash Card is ready to accept a new data transfer operation and held low when the card is busy. The Host memory card socket must provide a pull-up resistor. At power up and at Reset, the RDY/-BSY signal is held low (busy) until the CompactFlash Card has completed its power up or reset function. No access of any type should be made to the CompactFlash Card during this time. The RDY/-BSY signal is held high (disabled from being busy) whenever the following condition is true: The CompactFlash Card has been powered up with +RESET continuously disconnected or asserted.
-IREQ ( PC Card I/O Mode) INTRQ (True IDE Mode) -REG (PC Card Memory Mode) Attribute Memory Select -REG (PC Card I/O Mode) -DMACK (True IDE Mode) I 44
I/O Operation--After the CompactFlash Card has been configured for I/O operation, this signal is used as -Interrupt Request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE Mode, this signal is the active high Interrupt Request to the host. This signal is used during Memory Cycles to distinguish between Common Memory and Register (Attribute) Memory accesses. High for Common Memory, Low for Attribute Memory. The signal must also be active (low) during I/O Cycles when the I/O address is on the Bus. This signal is used by the host in response to DMARQ to initiate DMA transfers. NOTE: This signal may be negated by the host to suspend the DMS transfer in process. For Multiword DMA transfers, the device may negate DMARQ with the tL specified time once the DMACK- is asserted and reasserted again at a later time to resume DMA operation. Alternatively, if the device is able to continue the data transfer, the device may leave DMARQ asserted and wait for the host to reassert DMACK-. I 41 When the pin is high, this signal resets the CompactFlash Card. The card is Reset only at power up if this pin is left high or open from power-up. The card is also reset when the Soft Reset bit in the Card Configuration Option Register is set. This signal is the same as the PC Card Memory Mode signal. In the True IDE Mode this input pin is the active low hardware reset from the host. -13, 38 +5 V, +3.3 V power.
RESET (PC Card Memory Mode) RESET (PC Card I/O Mode) -RESET (True IDE Mode) VCC (PC Card Memory Mode)
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CompactFlash Memory Card Interface Description
Signal Name VCC (PC Card I/O Mode) VCC (True IDE Mode) -VS1 -VS2 (PC Card Memory Mode) -VS1 -VS2 (PC Card I/O Mode) -VS1 -VS2 (True IDE Mode) -WAIT (PC Card Memory Mode) -WAIT (PC Card I/O Mode) -IORDY (True IDE Mode) -WE (PC Card Memory Mode) -WE (PC Card I/O Mode) -WE (True IDE Mode) WP (PC Card Memory Mode) Write Protect -IOIS16 ( PC Card I/O Mode) -IOCS16 (True IDE Mode)
Dir.
Pin
Description This signal is the same for all modes. This signal is the same for all modes.
O
33 40
Voltage Sense Signals. -VS1 is grounded so that the CompactFlash Card CIS can be read at 3.3 volts and -VS2 is open and reserved by PCMCIA for a secondary voltage. This signal is the same for all modes.
This signal is the same for all modes.
O
42
SanDisk CompactFlash Memory Cards do not assert the -WAIT signal. SanDisk CompactFlash Memory Cards do not assert the -WAIT signal. SanDisk CompactFlash Memory Cards do not assert an -IORDY signal.
I
36
This is a signal driven by the host and used for strobing memory write data to the registers of the CompactFlash Card when the card is configured in the memory interface mode. It is also used for writing the configuration registers. In PC Card I/O Mode, this signal is used for writing the configuration registers. In True IDE Mode this input signal is not used and should be connected to VCC by the host.
O
24
Memory Mode--The CompactFlash Card does not have a write protect switch. This signal is held low after the completion of the reset initialization sequence. I/O Operation--When the CompactFlash Card is configured for I/O Operation, Pin 24 is used for the -I/O Selected is 16 Bit Port (-IOIS16) function. A Low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed port. In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer cycle.
3.3. Electrical Specification
The following table defines all D.C. Characteristics for the CompactFlash Memory Card Series. Unless otherwise stated, conditions are: Vcc = 5V 10% Vcc = 3.3V 5% Ta = 0C to 70C Absolute Maximum conditions are: Vcc = -0.3V min. to 7.0V max. V* = -0.5V min. to Vcc + 0.5V max.
* Voltage on any pin except Vcc with respect to GND.
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CompactFlash Memory Card Interface Description
3.3.1. Input Leakage Control
NOTE: In Table 3-3 x refers to the characteristics described in Section 3.3.2. For example, I1U indicates a pull up resistor with a type 1 input characteristic. Table 3-3. Input Leakage Control
Type IxZ IxU IxD Parameter Input Leakage Current Pull Up Resistor Pull Down Resistor Symbol IL RPU1 RPD1 Conditions Vih = Vcc/Vil = Gnd Vcc = 5.0V Vcc = 5.0V MIN -1 50k 50k TYP MAX 1 500k 500k Units A Ohm Ohm
NOTE: The minimum pullup resistor leakage current meets the PCMCIA specification of 10k ohms but is intentionally higher in the CompactFlash Memory Card Series product to reduce power use. 3.3.2. Input Characteristics
Table 3-4. Input Characteristics
Type Parameter Symbol MIN TYP VCC = 3.3 V 1 2 3 Input Voltage CMOS Input Voltage CMOS Input Voltage CMOS Schmitt Trigger Vih Vil Vih Vil Vth Vtl 2.4 1.5 1.8 1.0 0.6 0.6 4.0 2.0 2.8 2.0 MAX MIN TYP VCC = 5.0 V 0.8 0.8 Volts Volts Volts MAX Units
3.3.3. Output Drive Type In Table 3-5 "x" refers to the characteristics described in Section 3.3.4. For example, OT3 refers to Totempole output with a type-3 output drive characteristic. Table 3-5. Output Drive Type
Type OTx OZx OPx ONx Output Type Totempole Tri-State N-P Channel P-Channel Only N-Channel Only Valid Conditions Ioh & Iol Ioh & Iol Ioh Only Iol Only
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CompactFlash Memory Card Interface Description
3.3.4. Output Drive Characteristics
Table 3-6. Output Drive Characteristics
Type 1 Parameter Output Voltage Symbol Voh Vol 2 Output Voltage Voh Vol 3 Output Voltage Voh Vol X Tri-State Leakage Current Ioz Conditions Ioh = -4 mA Iol = 4 mA Ioh = -8 mA Iol = 8 mA Ioh = -8 mA Iol = 8 mA Vol = Gnd Voh = Vcc MIN Vcc -0.8V TYP MAX Units Volts Gnd +0.4V Volts Gnd +0.4V Volts Gnd +0.4V 10 A
Vcc -0.8V
Vcc -0.8V
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3.3.5. Power-up/Power-down Timing The timing specification in Table 3-7 was defined to permit peripheral cards to perform power-up initialization. Table 3-7. Power-up/Power-down Timing
Item Symbol Condition Min CE signal level1 Vi (CE) 0V 90% of (VCC - 5%)
Reset Width
ViMAX means Absolute Maximum Voltage for Input in the period of 0V 3-8
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tpr
tSU(VCC)
VCC Min. VIH 2V Hi-z th (Hi-z Reset) Reset tW(Reset) VCC VCC Min. trec tSU(Reset) tSU(Reset)
-CE1, -CE2 tW(Reset)
tpf
VIH 2V ts (Hi-z Reset) Hi-z
-CE1, -CE2
Figure 3-1. Power-Up/Power-Down Timing for Systems Supporting RESET
tpr VCC VCC Min. VIH 2V tSU(VCC)
-CE1, -CE2
Always Hi-z from system RESET Supplied by pull-up resistor on card (if present) tpf VCC VCC Min. trec VIH 2V -CE1, -CE2
Figure 3-2. Power-Up/Power-Down Timing for Systems Not Supporting RESET
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CompactFlash Memory Card Interface Description
3.3.6. Common Memory Read Timing Table 3-8. Common Memory Read Timing Specification for all Types of Memory
Speed Version tem Symbol IEEE Symbol 100 ns Min Read Cycle Time Address Access Time1 tc(R) ta(A) ta(CE) ta(OE) tdis(OE) tdis(CE) ten(CE) ten(OE) tv(A) tsu (A) th (A) tsu (CE) th (CE) tAVAV tAVQV tELQV tGLQV tGHQZ tEHQZ tELQNZ tGLQNZ tAXQX tAVGL tGHAX tELGL tGHEH 5 5 0 10 15 0 15 100 100 100 50 50 50 Max
Card Enable Access Time Output Enable Access Time Output Disable Time from -OE Output Disable Time from -CE Output Enable Time from -CE Output Enable Time from -OE Data Valid from Add Change1 Address Setup Time Address Hold Time Card Enable Setup Time Card Enable Hold Time
1. The -REG signal timing is identical to address signal timing. 2. SanDisk CompactFlash Memory Cards do not assert the -WAIT Signal. NOTE: All timings measured at the CompactFlash Memory Card. Skews and delays from the system driver/receiver to the CompactFlash Memory Card must be accounted for by the system.
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3.3.7. Common and Attribute Memory Write Timing The write timing specifications for Common and Attribute memory are the same. Table 3-9. Common and Attribute Memory Write Timing Specifications
Speed Version Item Symbol IEEE Symbol tAVAV tWLWH tAVWL tAVWH tELWH tDVWH tWMDX tWMAX tWLQZ tGHQZ tWHQNZ tGLQNZ tGHWL tWHGL tELWL tGHEH 5 5 10 10 0 15 100 ns Min 100 60 10 70 70 40 15 15 50 50 Max
Write Cycle Time Write Pulse Width Address Setup Time1 Address Setup Time for -WE1
tc(W) tw(WE) tsu(A) tsu(A-WEH) tsu(CE-WEH) tsu(D-WEH) th(D) trec(WE) tdis(WE) tdis(OE) ten(WE) ten(OE) tsu(OE-WE) th(OE-WE) tsu (CE) th (CE)
Card Enable Setup Time for -WE Data Setup Time from -WE Data Hold Time Write Recover Time Output Disable Time from -WE Output Disable Time from -OE Output Enable Time from -WE Output Enable Time from -OE Output Enable Setup from -WE Output Enable Hold from -WE Card Enable Setup Time Card Enable Hold Time
1. The -REG signal timing is identical to address signal timing. 2. SanDisk CompactFlash Memory Cards do not assert the -WAIT signal.
NOTE: All timings measured at the CompactFlash Memory Card. Skews and delays from the system driver/receiver to the CompactFlash Memory Card must be accounted for by the system.
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CompactFlash Memory Card Interface Description
3.3.8. Attribute Memory Read Timing Specification Table 3-10. Attribute Memory Read Timing Specification for all Types of Memory
Speed Version Item Symbol IEEE Symbol 300 ns Min Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Disable Time from -OE Output Enable Time from -OE Data Valid from Add Change Address Setup Time Address Hold Time Card Enable Setup Time Card Enable Hold Time tc(R) ta(A) ta(CE) ta(OE) tdis(OE) ten(OE) tv(A) tsu (A) th (A) tsu (CE) th (CE) tAVAV tAVQV tELQV tGLQV tGHQZ tGLQNZ tAXQX tAVGL tGHAX tELGL tGHEH 5 0 30 20 0 20 300 300 300 150 100 Min
1. SanDisk CompactFlash Memory Cards do not assert the -WAIT signal.
3.3.9. Memory Timing Diagrams
tc(R) ta(A) th(A)
A[10:0], -REG
ta(CE) tv(A) NOTE 1 th(CE) tdis(CE)
-CE
NOTE 1 tsu(A)
tsu(CE)
ten(CE) ta(OE)
-OE
tdis(OE)
DATA Valid
ten(OE)
D[15::0]
1. 2.
Shaded areas may be high or low. SanDisk CompactFlash Memory Cards do not assert the -WAIT signal. Figure 3-3. Common and Attribute Memory Read Timing Diagram
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tc(W)
A[10:0], -REG
tsu(CE-WEH)
-CE
NOTE 1
tsu(CE) tsu(A-WEH) th(CE) NOTE 4 tw(WE) trec(WE)
NOTE 1
-OE
NOTE 3
NOTE 4 tsu(A)
-WE
th(OE-WE) tsu(OE-WE) tsu(D-WEH)
DATA INPUT ESTABLISHED
th(D)
D[15::0](Din)
NOTE 2
tdis(OE)
tdis(WE) ten(WE)
ten(OE)
D[15::0](Dout)
1. 2. 3. 4.
Shaded areas may be high or low. When the data I/O pins are in the output state, no signals shall be applied to the data pins (D[15::0]) by the host system May be high or low for write timing, but restrictions on -OE from previous figures apply. SanDisk CompactFlash Memory Cards do not assert the -WAIT signal. Figure 3-4. Common and Attribute Memory Write Timing Diagram
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3.3.10. I/O Read (Input) Timing Specification
A[10:0]
thA(IORD)
-REG
tsuREG(IORD)
thREG(IORD)
-CE
tsuCE(IORD)
thCE(IORD)
-IORD
tsuA(IORD)
tw(IORD)
tdrINPACK(IORD)
-INPACK
tdfINPACK(IORD)
tdrIOIS16(ADR)
-IOIS16
tdfIOIS16(ADR)
td(IORD)
th(IORD)
D[15::0]
1. 2. 3. All timings are measured at the CompactFlash Memory Card. Skews and delays from the host system driver/receiver to the CompactFlash Memory Card must be accounted for by the system design. D[15::0] signifies data provided by the CompactFlash Memory Card to the host system.
Figure 3-5. I/O Read Timing Diagram
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CompactFlash Memory Card Interface Description
Table 3-11. I/O Read (Input) Timing Specification
Item Data Delay after -IORD Data Hold following -IORD -IORD Width Time Address Setup before -IORD Address Hold following -IORD -CE Setup before -IORD -CE Hold following -IORD -REG Setup before -IORD -REG Hold following -IORD -INPACK Delay Falling from -IORD -INPACK Delay Rising from -IORD -IOIS16 Delay Falling from Address -IOIS16 Delay Rising from Address 1. 2. Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tsuREG(IORD) thREG(IORD) tdfINPACK(IORD) tdrINPACK(IORD) tdfIOIS16(ADR) tdrIOIS16(ADR) IEEE Symbol tlGLQV tlGHQX tlGLIGH tAVIGL tlGHAX tELIGL tlGHEH tRGLIGL tlGHRGH tlGLIAL tlGHIAH tAVISL tAVISH 0 165 70 20 5 20 5 0 0 45 45 35 35 Min Max 100
All timings in ns. The maximum load on -INPACK and -IOIS16 is 1 LSTTL with 50 pF total load.
3.
SanDisk CompactFlash Memory Cards do not assert a -WAIT Signal.
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3.3.11. I/O Write (Output) Timing Specification
1. 2. 3.
All timings are measured at the CompactFlash Memory Card. Skews and delays from the host system driver/receiver to the CompactFlash Memory Card must be accounted for by the system design. D[15::0] signifies data provided by the host system to the CompactFlash Memory Card.
Figure 3-6. I/O Write Timing Diagram
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Table 3-12. I/O Write Timing Specification
Item Data Setup before -IOWR Data Hold following -IOWR -IOWR Width Time Address Setup before -IOWR Address Hold following -IOWR -CE Setup before -IOWR -CE Hold following -IOWR -REG Setup before -IOWR -REG Hold following -IOWR -IOIS16 Delay Falling from Address -IOIS16 Delay Rising from Address Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tsuREG(IOWR) thREG(IOWR) tdfIOIS16(ADR) tdrIOIS16(ADR) IEEE Symbol tDVIWL tlWHDX tlWLIWH tAVIWL tlWHAX tELIWL tlWHEH tRGLIWL tlWHRGH tAVISL tAVISH Min 60 30 165 70 20 5 20 5 0 35 35 Max
1.All timing in ns. 2.The maximum load on -IOIS16 is 1 LSTTL with 50 pF total load.
3.3.12. True IDE Mode
The following sections provide valuable information for the True IDE mode.
3.3.12.1. Deskewing The host shall provide cable deskewing for all signals originating from the device. The device shall provide cable deskewing for all signals originating at the host. All timing values and diagrams are shown and measured at the connector of the selected device. 3.3.12.2. Transfer Timing The minimum cycle time supported by devices in PIO mode 3, 4 and Multiword DMA mode 1, 2 respectively shall always be greater than or equal to the minimum cycle time defined by the associated mode, e.g., a device supporting PIO mode 4 timing shall not report a value less than 120 ns. The minimum cycle time defined for PIO mode 4 timings. Register Transfers Figure 3-7 defines the relationships between the interface signals for register transfers. For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 3-9 defines the minimum value that shall be placed in word 68.
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t0
ADDR valid (See note 1)
t1
t2
t9 t2i
IORD-/IOWR-
WRITE DD(7:0) (See note 2)
t3 t4
READ DD(7:0) (See note 2)
t5 t6 t6z
1. 2. 3. 4.
Device address consists of signals -CS0, -CS1 and -DA(2:0). Data consists of DD(7:0). SanDisk CompactFlash Memory Cards do not assert an -IORDY signal. All signals are shown with the asserted condition facing the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition. Figure 3-7. Register Transfer To/From Device Table 3-13. Register Transfer To/From Device
PIO Timing Parameters t0 t1 t2 t2i t3 t4 t5 t6 t6z t9 Cycle time Address valid to IORD-/IOWR- setup IORD-/IOWR- pulse width 8-bit IORD-/IOWR- recovery time IOWR- data setup IOWR- data hold IORD- data setup IORD- data hold IORD- data tri-state IORD-/IOWR- to address valid hold (min) (min) (min) (min) (min) (min) (min) (min) (max) (min) Mode 4 ns 120 25 70 25 20 10 20 5 30 10 2 1 1 Note 1
1. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i shall be met. The minimum total cycle time requirements are greater than the sum of t2 and t2i. This means a host implementation may lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
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2. This parameter specifies the time from the negation edge of /IORD to the time that the data bus is no longer driven by the device (tri-state). 3. SanDisk CompactFlash Memory Cards do not assert an -IORDY signal. PIO Data Transfers Figure 3-8 defines the relationships between the interface signals for PIO data transfers. For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 3-10 defines the minimum value that shall be placed in word 68.
t0
ADDR valid (See note 1)
t1
t2
t9 t2i
IORD-/IOWR-
WRITE DD(15:0) (See note 2)
t3 t4
READ DD(15:0) (See note 2)
t5
t6 t6z
1. 2. 3. 4.
Device address consists of signals -CS0, -CS1 and -DA(2:0). Data consists of DD(15:0). SanDisk CompactFlash Memory Cards do not assert an -IORDY signal. All signals are shown with the asserted condition facing the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition. Figure 3-8. PIO Data Transfer To/From Device
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Table 3-14. PIO Data Transfer To/From Device
PIO Timing Parameters t0 t1 t2 t2i t3 t4 t5 t6 t6z t9 Cycle time Address valid to IORD-/IOWR- setup IORD-/IOWR- pulse width 16-bit IORD-/IOWR- recovery time IOWR- data setup IOWR- data hold IORD- data setup IORD- data hold IORD- data tri-state IORD-/IOWR- to address valid hold (min) (min) (min) (min) (min) (min) (min) (min) (max) (min) Mode 0 ns 600 70 165 60 30 50 5 30 20 Mode 1 ns 383 50 125 45 20 35 5 30 15 Mode 2 ns 240 30 100 30 15 20 5 30 10 Mode 3 ns 180 30 80 70 30 10 20 5 30 10 Mode 4 ns 120 25 70 25 20 10 20 5 30 10 2 1 1 Note 1
1. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i shall be met. The minimum total cycle time requirements are greater than the sum of t2 and t2i. This means a host implementation may lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. 2. This parameter specifies the time from the negation edge of /IORD to the time that the data bus is no longer driven by the device (tri-state). 3. SanDisk CompactFlash Memory Cards do not assert an -IORDY signal.
3.4. Card Configuration
The CompactFlash Memory Cards are identified by appropriate information in the Card Information Structure (CIS). The following configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In addition, these registers provide a method for accessing status information about the CompactFlash Card that may be used to arbitrate between multiple interrupt sources on the same interrupt level or to replace status information that appears on dedicated pins in memory cards that have alternate use in I/O cards.
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Table 3-15. Registers and Memory Space Decoding
-CE2 1 X 1 0 0 X 1 0 0 X 1 1 1 0 0 -CE1 1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 -REG X 0 1 1 1 0 1 1 1 0 0 0 0 0 0 -OE -WE X 0 0 0 0 1 1 1 1 0 1 0 1 0 1 X 1 1 1 1 0 0 0 0 1 0 1 0 1 0 A10 X X X X X X X X X 0 0 X X X X A9 X 1 X X X 1 X X X 0 0 X X X X A8-A4 XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX A3 X X X X X X X X X X X X X X X A2 X X X X X X X X X X X X X X X A1 X X X X X X X X X X X X X X X A0 X 0 X X 0 0 X X 0 0 0 1 1 X X Standby Configuration Registers Read Common Memory Read (8 Bit D7-D0) Common Memory Read (8 Bit D15-D8) Common Memory Read (16 Bit D15-D0) Configuration Registers Write Common Memory Write (8 Bit D7-D0) Common Memory Write (8 Bit D15-D8) Common Memory Write (16 Bit D15-D0) Card Information Structure Read Invalid Access (CIS Write) Invalid Access (Odd Attribute Read) Invalid Access (Odd Attribute Write) Invalid Access (Odd Attribute Read) Invalid Access (Odd Attribute Write) SELECTED SPACE
Table 3-16. Configuration Registers Decoding
-CE2 X X X X X X X X -CE1 0 0 0 0 0 0 0 0 -REG 0 0 0 0 0 0 0 0 -OE 0 1 0 1 0 1 0 1 -WE 1 0 1 0 1 0 1 0 A10 0 0 0 0 0 0 0 0 A9 1 1 1 1 1 1 1 1 A8-A4 00 00 00 00 00 00 00 00 A3 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 0 0 0 0 0 0 0 SELECTED REGISTER Configuration Option Reg Read Configuration Option Reg Write Card Status Register Read Card Status Register Write Pin Replacement Register Read Pin Replacement Register Write Socket and Copy Register Read Socket and Copy Register Write
NOTE: The location of the card configuration registers should always be read from the CIS since these locations may vary in future products. No writes should be performed to the CompactFlash Memory Card attribute memory except to the card configuration register addresses. All other attribute memory locations are reserved. 3.4.1. Attribute Memory Function Attribute memory is a space where CompactFlash Memory Card identification and configuration information is stored, and is limited to 8-bit wide accesses only at even addresses. The card configuration registers are also located here.
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For the Attribute Memory Read function, signals -REG and -OE must be active and -WE inactive during the cycle. As in the Main Memory Read functions, the signals -CE1 and -CE2 control the even-byte and odd-byte address, but only the even-byte data is valid during the Attribute Memory access. Refer to Table 3-12 below for signal states and bus validity for the Attribute Memory function. Table 3-17. Attribute Memory Function
Function Mode Standby Mode Read Byte Access CIS ROM (8 bits) Write Byte Access CIS (8 bits) (Invalid) Read Byte Access Configuration (8 bits) Write Byte Access Configuration (8 bits) Read Word Access CIS (16 bits) Write Word Access CIS (16 bits) (Invalid) Read Word Access Configuration (16 bits) Write Word Access Configuration (16 bits) -REG X L L L L L L L L -CE2 H H H H H L L L L -CE1 H L L L L L L L L A9 X L L H H L L H H A0 X L L L L X X X X -OE X L H L H L H L H -WE X H L H L H L H L D15-D8 High Z High Z Do not care High Z Do not care Not Valid Do not care Not Valid Do not care D7-D0 High Z Even Byte Even Byte Even Byte Even Byte Even Byte Even Byte Even Byte Even Byte
NOTE: The -CE signal or both the -OE signal and the -WE signal must be de-asserted between consecutive cycle operations. 3.4.2. Configuration Option Register (Address 200h in Attribute Memory) The Configuration Option Register is used to configure the cards interface, address decoding and interrupt and to issue a soft reset to the CompactFlash Memory Card.
Operation R/W SRESET D7 SRESET D6 LevlREQ D5 Conf5 D4 Conf4 D3 Conf3 D2 Conf2 D1 Conf1 D0 Conf0
LevlREQ Conf5--Conf0
Soft Reset--Setting this bit to one (1), waiting the minimum reset width time and returning to zero (0) places the CompactFlash Memory Card in the Reset state. Setting this bit to one (1) is equivalent to assertion of the +RESET signal except that the SRESET bit is not cleared. Returning this bit to zero (0) leaves the CompactFlash Memory Card in the same un-configured, Reset state as following power-up and hardware reset. This bit is set to zero (0) by power-up and hardware reset. Using the PCMCIA Soft Reset is considered a hard Reset by the ATA Commands. Contrast with Soft Reset in the Device Control Register. This bit is set to one (1) when Level Mode Interrupt is selected, and zero (0) when Pulse Mode is selected. Set to zero (0) by Reset. Configuration Index. Set to zero (0) by reset. It's used to select operation mode of the CompactFlash Memory Card as shown below.
NOTE: Conf5 and Conf4 are reserved and must be written as zero (0).
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Table 3-18. Card Configurations
Conf5 0 0 0 0 Conf4 0 0 0 0 Conf3 0 0 0 0 Conf2 0 0 0 0 Conf1 0 0 1 1 Conf0 0 1 0 1 Memory Mapped I/O Mapped, Any 16 byte system decoded boundary I/O Mapped, 1F0-1F7/3F6-3F7 I/O Mapped, 170-177/376-377 Disk Card Mode
3.4.3. Card Configuration and Status Register (Address 202h in Attribute Memory) The Card Configuration and Status Register contain information about the Card's condition. Table 3-19. Card Configuration and Status Register Organization
Operation Read Write Changed D7 Changed 0 D6 SigChg SigChg D5 IOis8 IOis8 D4 0 0 D3 0 0 D2 PwrDwn PwrDwn D1 Int 0 D0 0 0
Indicates that one or both of the Pin Replacement register CRdy, or CWProt bits are set to one (1). When the Changed bit is set, -STSCHG Pin 46 is held low if the SigChg bit is a One (1) and the CompactFlash Memory Card is configured for the I/O interface. This bit is set and reset by the host to enable and disable a state-change "signal" from the Status Register, the Changed bit control pin 46 the Changed Status signal. If no state change signal is desired, this bit should be set to zero (0) and pin 46 (-STSCHG) signal will be held high while the CompactFlash Memory Card is configured for I/O. The host sets this bit to a one (1) if the CompactFlash Memory Card is to be configured in an 8 bit I/O mode. The CompactFlash Card is always configured for both 8- and 16-bit I/O, so this bit is ignored. This bit indicates whether the host requests the CompactFlash Memory Card to be in the power saving or active mode. When the bit is one (1), the CompactFlash Card enters a power down mode. When zero (0), the host is requesting the CompactFlash Card to enter the active mode. The PCMCIA Rdy/-Bsy value becomes BUSY when this bit is changed. Rdy/-Bsy will not become Ready until the power state requested has been entered. The CompactFlash Card automatically powers down when it is idle and powers back up when it receives a command. This bit represents the internal state of the interrupt request. This value is available whether or not I/O interface has been configured. This signal remains true until the condition that caused the interrupt request has been serviced. If interrupts are disabled by the -IEN bit in the Device Control Register, this bit is a zero (0).
SigChg
IOis8 PwrDwn
Int
3.4.4. Pin Replacement Register (Address 204h in Attribute Memory)
Table 3-20. Pin Replacement Register
Operation Read Write CRdy/-Bsy CWProt D7 0 0 D6 0 0 D5 CRdy/-Bsy CRdy/-Bsy D4 CWProt CWProt D3 1 0 D2 1 0 D1 RRdy/-Bsy MRdy/-Bsy D0 RWProt MWProt
This bit is set to one (1) when the bit RRdy/-Bsy changes state. This bit can also be written by the host. This bit is set to one (1) when the RWprot changes state. This bit may also be written by the host.
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RRdy/-Bsy
This bit is used to determine the internal state of the Rdy/-Bsy signal. This bit may be used to determine the state of the Ready/-Busy as this pin has been reallocated for use as Interrupt Request on an I/O card. When written, this bit acts as a mask for writing the corresponding bit CRdy/-Bsy. This bit is always zero (0) since the CompactFlash Memory Card does not have a Write Protect switch. When written, this bit acts as a mask for writing the corresponding bit CWProt. This bit acts as a mask for writing the corresponding bit CRdy/-Bsy. This bit when written acts as a mask for writing the corresponding bit CWProt.
RWProt MRdy/-Bsy MWProt
Table 3-21. Pin Replacement Changed Bit/Mask Bit Values
Initial Value of (C) Status 0 1 X X Written by Host "C" Bit X X 0 1 "M" Bit 0 0 1 1 Final "C" Bit 0 1 0 1 Comments
Unchanged Unchanged Cleared by Host Set by Host
3.4.5. Socket and Copy Register (Address 206h in Attribute Memory This register contains additional configuration information. This register is always written by the system before writing the card's Configuration Index Register. Table 3-22. Socket and Copy Register Organization
Operation Read Write Reserved Drive # X D7 Reserved 0 D6 0 0 D5 0 0 D4 Drive # Drive # (0) D3 0 X D2 0 X D1 0 X D0 0 X
This bit is reserved for future standardization. This bit must be set to zero (0) by the software when the register is written. This bit indicates the drive number of the card if twin card configuration is supported. The socket number is ignored by the CompactFlash Memory Card.
3.5. I/O Transfer Function
The following sections provide valuable information for the I/O Transfer function.
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3.5.1. I/O Function The I/O transfer to or from the CompactFlash Memory Card can be either 8 or 16 bits. When a 16-bit accessible port is addressed, the signal -IOIS16 is asserted by the CompactFlash Card. Otherwise, the -IOIS16 signal is de-asserted. When a 16-bit transfer is attempted, and the -IOIS16 signal is not asserted by the CompactFlash Card, the system must generate a pair of 8-bit references to access the word`s even byte and odd byte. The CompactFlash Card permits both 8 and 16 bit accesses to all of its I/O addresses, so -IOIS16 is asserted for all addresses to which the CompactFlash Card responds. Table 3-23. I/O Function
Function Code Standby Mode Byte Input Access (8 bits) Byte Output Access (8 bits) Word Input Access (16 bits) Word Output Access (16 bits) I/O Read Inhibit I/O Write Inhibit High Byte Input Only (8 bits) High Byte Output Only (8 bits) -REG X L L L L L L H H L L -CE2 H H H H H L L X X L L -CE1 H L L L L L L X X H H A0 X L H L H L L X X X X -IORD X L L H H L H L H L H -IOWR X H H L L H L H L H L D15-D8 High Z High Z High Z Do not care Do not care Odd-Byte Odd-Byte Do not care High Z Odd-Byte Odd-Byte D7-D0 High Z Even-Byte Odd-Byte Even-Byte Odd-Byte Even-Byte Even-Byte Do not care High Z High Z Do not care
3.6. Common Memory Transfer Function
This section contains valuable information on the Common Memory Transfer function. 3.6.1. Common Memory Function The Common Memory transfer to or from the CompactFlash Memory Card can be either 8 or 16 bits. The CompactFlash Memory Card permits both 8 and 16 bit accesses to all of its Common Memory addresses.
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Table 3-24. Common Memory Function
Function Code Standby Mode Byte Read Access (8 bits) Byte Write Access (8 bits) Word Read Access (16 bits) Word Write Access (16 bits) Odd Byte Read Only (8 bits) Odd Byte Write Only (8 bits) -REG X H H H H H H H H -CE2 H H H H H L L L L -CE1 H L L L L L L H H A0 X L H L H X X X X -OE X L L H H L H L H -WE X H H L L H L H L D15-D8 High Z High Z High Z Do not care Do not care Odd-Byte Odd-Byte Odd-Byte Odd-Byte D7-D0 High Z Even-Byte Odd-Byte Even-Byte Odd-Byte Even-Byte Even-Byte High Z Do not care
3.7. True IDE Mode I/O Transfer Function
This section contains valuable information on the True IDE Mode I/O Transfer function. 3.7.1. True IDE Mode I/O Function The CompactFlash Memory Card can be configured in a True IDE Mode of operation. This CompactFlash Card is configured in this mode only when the -OE input signal is grounded by the host when power is applied to the card. In this True IDE Mode, the PCMCIA protocol and configuration are disabled and only I/O operations to the Task File and Data Register are allowed. In this mode, no Memory or Attribute Registers are accessible to the host. CompactFlash Cards permit 8 bit data accesses if the user issues a Set Feature Command to put the device in 8-bit Mode. NOTE: Removing and reinserting the CompactFlash Memory Card while the host computer's power is on will reconfigure the CompactFlash Card to PC Card ATA mode from the original True IDE Mode. To configure the CompactFlash Card in True IDE Mode, the 50-pin socket must be power cycled with the CompactFlash Card inserted and -OE (output enable) grounded by the host. Table 3-25 defines the function of the operations for the True IDE Mode. Table 3-25. IDE Mode I/O Function
Function Code Invalid Mode Standby Mode Task File Write Task File Read Data Register Write Data Register Read Control Register Write Alt Status Read -CE2 L H H H H H L L -CE1 L H L L L L H H A0 X X 1-7h 1-7h 0 0 6h 6h -IORD X X H L H L H L -IOWR X X L H L H L H D15-D8 High Z High Z Do not care High Z Odd-Byte In Odd-Byte Out Do not care High Z D7-D0 High Z High Z Data In Data Out Even-Byte In Even-Byte Out Control In Status Out
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4. ATA Drive Register Set Definition and Protocol
The CompactFlash Memory Card can be configured as a high performance I/O device through the following ways:
* * *
Standard PC-AT disk I/O address spaces 1F0h-1F7h, 3F6h-3F7h (primary); 170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ). Any system decoded 16-byte I/O block using any available IRQ. Memory space.
The communication to or from the CompactFlash Memory Card is done using the Task File registers, which provide all the necessary registers for control and status information. The PCMCIA interface connects peripherals to the host using four register mapping methods. Table 4-1 is a detailed description of these methods. Table 4-1. I/O Configurations
Standard Configurations Config Index 0 1 2 2 3 3 IO or Memory Memory I/O I/O I/O I/O I/O Address 0-F, 400-7FF XX0-XXF 1F0-1F7, 3F6-3F7 1F0-1F7, 3F6-3F7 170-177, 376-377 170-177, 376-377 Drive # 0 0 0 1 0 1 Description Memory Mapped I/O Mapped 16 Contiguous Registers Primary I/O Mapped Drive 0 Primary I/O Mapped Drive 1 Secondary I/O Mapped Drive 0 Secondary I/O Mapped Drive 1
4.1. I/O Primary and Secondary Address Configurations
Table 4-2. Primary and Secondary I/O Decoding
-REG 0 0 0 0 0 0 0 0 0 0 A9-A4 1F(17) 1F(17) 1F(17) 1F(17) 1F(17) 1F(17) 1F(17) 1F(17) 3F(37) 3F(37) A3 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD=0 Even RD Data Error Register Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Status Alt Status Drive Address -IOWR=0 Even WR Data Features Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Command Device Control Reserved Note 1, 2 1
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1. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Do not care) as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. 2. A byte access to register 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register.
4.2. Contiguous I/O Mapped Addressing
When the system decodes a contiguous block of I/O registers to select the CompactFlash Memory Card, the registers are accessed in the block of I/O space decoded by the system as follows: Table 4-3. Contiguous I/O Decoding
-REG 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 1 0 1 Offset 0 1 2 3 4 5 6 7 8 9 D E F -IORD=0 Even RD Data Error Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Status Dup Even RD Data Dup. Odd RD Data Dup. Error Alt Status Drive Address -IOWR=0 Even WR Data Features Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Command Dup. Even WR Data Dup. Odd WR Data Dup. Features Device Ctl Reserved 2 2 2 Notes 1 2
NOTES: 1. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Do not care) as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. A byte access to register 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register. 2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even than odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9 access only the odd byte of the data. 3. Address lines that are not indicated are ignored by the CompactFlash Memory Card for accessing all the registers in this table.
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4.3. Memory Mapped Addressing
When the CompactFlash Memory Card registers are accessed via memory references, the registers appear in the common memory space window: 0-2K bytes as shown in Table 4-4. Table 4-4. Memory Mapped Decoding
-REG 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A9-A4 X X X X X X X X X X X X X X X A3 0 0 0 0 0 0 0 0 1 1 1 1 1 X X A2 0 0 0 0 1 1 1 1 0 0 1 1 1 X X A1 0 0 1 1 0 0 1 1 0 0 0 1 1 X X A0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 Offset 0 1 2 3 4 5 6 7 8 9 D E F 8 9 -OE=0 Even RD Data Error Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Status Dup. Even RD Data Dup. Odd RD Data Dup. Error Alt Status Drive Address Even RD Data Odd RD Data -WE=0 Even WR Data Features Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Command Dup. Even WR Data Dup. Odd WR Data Dup. Features Device Ctl Reserved Even WR Data Odd WR Data 3 3 2 2 2 Notes 1 2
NOTES: 1. Register 0 is accessed with -CE1 low and -CE2 low as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. A byte access to address 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register. 2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even then odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9 access only the odd byte of the data. 3. Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h and 7FFh access register 9. This 1 KByte memory window to the data register is provided so that hosts can perform memory to memory block moves to the data register when the register lies in memory space. Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory to memory block move instruction. Some PCMCIA socket adapters also have auto incrementing address logic embedded within them. This address window allows these hosts and adapters to function efficiently. Note that this entire window accesses the Data Register FIFO and does not allow random access to the data buffer within the CompactFlash Memory Card.
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4.4. True IDE Mode Addressing
When the CompactFlash Memory Card is configured in the True IDE Mode the I/O decoding is as listed in Table 4-5. Table 4-5. True IDE Mode I/O Decoding
-CE2 1 1 1 1 1 1 1 1 0 0 -CE1 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD=0 Even RD Data Error Register Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Status Alt Status Drive Address -IOWR=0 Even WR Data Features Sector Count Sector No. Cylinder Low Cylinder High Select Card/Head Command Device Control Reserved
4.5. ATA Registers
NOTE: In accordance with the PCMCIA specification: each of the registers below which is located at an odd offset address may be accessed at its normal address and also the corresponding even address (normal address -1) using data bus lines (D15-D8) when -CE1 is high and -CE2 is low unless -IOIS16 is high (not asserted) and an I/O cycle is being performed. 4.5.1. Data Register (Address--1F0[170];Offset 0, 8, 9) The Data Register is a 16-bit register, and it is used to transfer data blocks between the CompactFlash Memory Card data buffer and the Host. This register overlaps the Error Register. The table below describes the combinations of data register access and is provided to assist in understanding the overlapped Data Register and Error/Feature Register rather than to attempt to define general PCMCIA word and byte access modes and operations. See the PCMCIA PC Card Standard Release 2.0 for definitions of the Card Accessing Modes for I/O and Memory cycles. NOTE: Because of the overlapped registers, access to the 1F1, 171 or offset 1 are not defined for word (-CE2 = 0 and -CE1 = 0) operations. SanDisk products treat these accesses as accesses to the Word Data Register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on the operations that can be performed by the socket.
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Table 4-6. Data Register
Data Register Word Data Register Even Data Register Odd Data Register Odd Data Register Error/Feature Register Error/Feature Register Error/Feature Register CE20 1 1 0 1 0 0 CE10 0 0 1 0 1 0 A0 X 0 1 X 1 X X Offset 0,8,9 0,8 9 8,9 1, Dh 1 Dh Data Bus D15-D0 D7-D0 D7-D0 D15-D8 D7-D0 D15-D8 D15-D8
4.5.2. Error Register (Address--1F1[171]; Offset 1, 0Dh Read Only) This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. The bits are defined as follows:
D7 BBK D6 UNC D5 0 D4 IDNF D3 0 D2 ABRT D1 0 D0 AMNF
This register is also accessed on data bits D15-D8 during a write operation to offset 0 with -CE2 low and -CE1 high.
Bit 7 (BBK) Bit 6 (UNC) Bit 5 Bit 4 (IDNF) Bit 3 Bit 2 (Abort) Bit 1 Bit 0 (AMNF) This bit is set when a Bad Block is detected. This bit is set when an Uncorrectable Error is encountered. This bit is 0. The requested sector ID is in error or cannot be found. This bit is 0. This bit is set if the command has been aborted because of a CompactFlash Memory Card status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued. This bit is 0. This bit is set in case of a general error.
4.5.3. Feature Register (Address--1F1[171]; Offset 1, 0Dh Write Only This register provides information regarding features of the CompactFlash Memory Card that the host can utilize. This register is also accessed on data bits D15-D8 during a write operation to Offset 0 with -CE2 low and -CE1 high. 4.5.4. Sector Count Register (Address--1F2[172]; Offset 2) This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the CompactFlash Memory Card. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request. 4.5.5. Sector Number (LBA 7-0) Register (Address--1F3[173]; Offset 3) This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any CompactFlash Memory Card data access for the subsequent command.
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4.5.6. Cylinder Low (LBA 15-8) Register (Address--1F4[174]; Offset 4) This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the Logical Block Address. 4.5.7. Cylinder High (LBA 23-16) Register (Address--1F5[175]; Offset 5) This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address. 4.5.8. Drive/Head (LBA 27-24) Register (Address 1F6[176]; Offset 6) The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. The bits are defined as follows:
D7 1 Bit 7 Bit 6 D6 LBA D5 1 D4 DRV D3 HS3 D2 HS2 D1 HS1 D0 HS0
Bit 5 Bit 4 (DRV) Bit 3 (HS3) Bit 2 (HS2) Bit 1 (HS1) Bit 0 (HS0)
This bit is set to 1. LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is selected. In Logical Block Mode, the Logical Block Address is interpreted as follows: LBA07-LBA00: Sector Number Register D7-D0. LBA15-LBA08: Cylinder Low Register D7-D0. LBA23-LBA16: Cylinder High Register D7-D0. LBA27-LBA24: Drive/Head Register bits HS3-HS0. This bit is set to 1. This bit will have the following meaning. DRV is the drive number. When DRV=0, drive (card) 0 is selected When DRV=1, drive (card) 1 is selected. The CompactFlash Card is set to be Card 0 or 1 using the copy field of the PCMCIA Socket & Copy configuration register. When operating in the Cylinder , Head, Sector mode, this is bit 3 of the head number. It is Bit 27 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode.
4.5.9. Status & Alternate Status Registers (Address 1F7[177]&3F6[376]; Offsets 7 & Eh) These registers return the CompactFlash Memory Card status when read by the host. Reading the Status register does clear a pending interrupt while reading the Auxiliary Status register does not. The meaning of the status bits are described as follows:
D7 BUSY D6 RDY D5 DWF D4 DSC D3 DRQ D2 CORR D1 0 D0 ERR
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Bit 7 (BUSY)
Bit 6 (RDY) Bit 5 (DWF) Bit 4 (DSC) Bit 3 (DRQ) Bit 2 (CORR) Bit 1 (IDX) Bit 0 (ERR)
The busy bit is set when the CompactFlash Memory Card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. RDY indicates whether the device is capable of performing CompactFlash Memory Card operations. This bit is cleared at power up and remains cleared until the CompactFlash Card is ready to accept a command. This bit, if set, indicates a write fault has occurred. This bit is set when the CompactFlash Memory Card is ready. The Data Request is set when the CompactFlash Memory Card requires that information be transferred either to or from the host through the Data register. This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation. This bit is always set to 0. This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error.
4.5.10. Device Control Register (Address--3F6[376]; Offset Eh) This register is used to control the CompactFlash Memory Card interrupt request and to issue an ATA soft reset to the card. The bits are defined as follows:
D7 X Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 (SW Rst) D6 X D5 X D4 X D3 1 D2 SW Rst D1 -IEn D0 0
Bit 1 (-IEn) Bit 0
This bit is an X (Do not care). This bit is an X (Do not care). This bit is an X (Do not care). This bit is an X (Do not care). This bit is ignored by the CompactFlash Memory Card. This bit is set to 1 in order to force the CompactFlash Memory Card to perform an AT Disk controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers (4.3.2 to 4.3.5) as a hardware Reset does. The Card remains in Reset until this bit is reset to '0'. The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the CompactFlash Memory Card are disabled. This bit also controls the Int bit in the Configuration and Status Register. This bit is set to 0 at power on and Reset. This bit is ignored by the CompactFlash Memory Card.
4.5.11. Card (Drive) Address Register (Address 3F7[377]; Offset Fh) This register is provided for compatibility with the AT disk drive interface. It is recommended that this register not be mapped into the host's I/O space because of potential conflicts on Bit 7. The bits are defined as follows:
D7 X Bit 7 D6 -WTG D5 -HS3 D4 -HS2 D3 -HS1 D2 -HS0 D1 -nDS1 D0 -nDS0
This bit is unknown. Implementation Note: Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller operating at the same addresses as the CompactFlash Memory Card. Following are some possible solutions to this problem for the PCMCIA implementation: 1. Locate the CompactFlash Memory Card at a non-conflicting address, i.e., Secondary address (377) or in an independently decoded Address Space when a Floppy Disk Controller is located at the Primary addresses. 2. Do not install a Floppy and a CompactFlash Memory Card in the system at the same time.
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Bit 6 (-WTG) Bit 5 (-HS3) Bit 4 (-HS2) Bit 3 (-HS1) Bit 2 (-HS0) Bit 1 (-nDS1) Bit 0 (-nDS0)
3. Implement a socket adapter that can be programmed to (conditionally) tri-state D7 of I/0 address 3F7/377 when a CompactFlash Memory Card is installed and conversely to tri-state D6-D0 of I/O address 3F7/377 when a floppy controller is installed. 4. Do not use the CompactFlash Memory Card's Drive Address register. This may be accomplished by either a) If possible, program the host adapter to enable only I/O addresses 1F0-1F7, 3F6 (or 170-177, 176) to the CompactFlash Memory Card or b) if provided use an additional Primary/Secondary configuration in the CompactFlash Card which does not respond to accesses to I/O locations 3F7 and 377. With either of these implementations, the host software must not attempt to use information in the Drive Address Register. This bit is 0 when a write operation is in progress, otherwise, it is 1. This bit is the negation of bit 3 in the Drive/Head register. This bit is the negation of bit 2 in the Drive/Head register. This bit is the negation of bit 1 in the Drive/Head register. This bit is the negation of bit 0 in the Drive/Head register. This bit is 0 when drive 1 is active and selected. This bit is 0 when the drive 0 is active and selected.
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5. ATA Command Description
This section defines the software requirements and the format of the commands the host sends to the CompactFlash Memory Cards. Commands are issued to the CompactFlash Card by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command Register. The manner in which a command is accepted varies. There are three classes (see Table 5-1) of command acceptance, all dependent on the host not issuing commands unless the CompactFlash Card is not busy. (The BUSY bit in the status and alternate status registers is 0.)
* *
*
Upon receipt of a Class 1 command, the CompactFlash Card sets the BUSY bit within 400 nsec. Upon receipt of a Class 2 command, the CompactFlash Memory Card sets the BUSY bit within 400 nsec, sets up the sector buffer for a write operation, sets DRQ within 700 sec, and clears the BUSY bit within 400 nsec of setting DRQ. Upon receipt of a Class 3 command, the CompactFlash Memory Card sets the BUSY bit within 400 nsec, sets up the sector buffer for a write operation, sets DRQ within 20 msec (assuming no reassignments), and clears the BUSY bit within 400 nsec of setting DRQ.
5.1. ATA Command Set
Table 5-1 summarizes the ATA command set with the paragraphs that follow describing the individual commands and the task file for each. Table 5-1. ATA Command Set
Class 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 COMMAND Check Power Mode Execute Drive Diagnostic Erase Sector(s) (Note 2) Format Track Identify Drive Idle Idle Immediate Initialize Drive Parameters Read Buffer Read Multiple Read Long Sector Read Sector(s) Read Verify Sector(s) Recalibrate Request Sense (Note 1) Seek Set Features Set Multiple Mode Set Sleep Mode Stand By Stand By Immediate 90h C0h 50h ECh E3h or 97h E1h or 95h 91h E4h C4h 22h or 23h 20h or 21h 40h or 41h 1Xh 03h 7Xh EFh C6h E6h or 99h E2h or 96h E0h or 94h Code E5h or 98h FR Y SC Y Y Y Y Y Y Y Y SN Y Y Y Y Y Y CY Y Y Y Y Y Y Y DH D D Y Y D D D Y D Y Y Y Y D D Y D D D D D LBA Y Y Y Y Y Y Y -
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ATA Command Description
Class 1 1 2 2 3 3 2 2 2 Note 1: Note 2:
COMMAND Translate Sector (Note 1) Wear Level (Note 1) Write Buffer Write Long Sector Write Multiple Write Multiple w/o Erase (Note 2) Write Sector(s) Write Sector(s) w/o Erase (Note 2) Write Verify Sector(s) 87h F5h E8h
Code
FR -
SC Y Y Y Y Y Y
SN Y Y Y Y Y Y Y
CY Y Y Y Y Y Y Y
DH Y Y D Y Y Y Y Y Y
LBA Y Y Y Y Y Y Y
32h or 33h C5h CDh 30h or 31h 38h 3Ch
These commands are not standard PC Card ATA commands but provide additional functionality. These commands are not standard PC Card ATA commands and these features are no longer supported with the introduction of 256 Mbit Flash Technology. If one of these commands is issued, the sectors will be erased but there will be no net gain in write performance when using the Write Without Erase command. Definitions: FR = Features Register, SC = Sector Count Register, SN = Sector Number Register, CY = Cylinder Registers, DH = Card/Drive/Head Register, LBA = Logical Block Address Mode Supported (see command descriptions for use). Y--The register contains a valid parameter for this command. For the Drive/Head Register Y means both the CompactFlash Card and head parameters are used; D--only the CompactFlash Card parameter is valid and not the head parameter.
5.1.1. Check Power Mode--98H, E5H Table 5-2. Check Power Mode
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 E5H or 98H Drive X X X X X X 3 2 1 0
This command checks the power mode. If the CompactFlash Memory Card is in, going to, or recovering from the sleep mode, the CompactFlash Card sets BSY, sets the Sector Count Register to 00h, clears BSY and generates an interrupt. If the CompactFlash Memory Card is in Idle mode, the CompactFlash Card sets BSY, sets the Sector Count Register to FFh, clears BSY and generates an interrupt.
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5.1.2. Execute Drive Diagnostic--90H Table 5-3. Executive Drive Diagnostic
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 90H X 3 2 1 0
This command performs the internal diagnostic tests implemented by the CompactFlash Memory Card. The Diagnostic codes shown in Table 5-4 are returned in the Error Register at the end of the command. Table 5-4. Diagnostic Codes
Code 01h 02h 03h 04h 05h 8Xh Error Type No Error Detected Formatter Device Error Sector Buffer Error ECC Circuitry Error Controlling Microprocessor Error Slave Failed (True IDE Mode)
5.1.3. Erase Sector(s)--C0H
Table 5-5. Erase Sectors
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 C0H Head (LBA 27-24) 3 2 1 0
This command is no longer recommended. There is essentially no net gain in the use of the Erase Sectors Command and/or the Write Without Erase Commands. This command is supported to guarantee backward compatibility.
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5.1.4. Format Track--50H Table 5-6. Format Track
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) X (LBA 7-0) Count (LBA mode only) X 7 6 5 4 50H Head (LBA 27-24) 3 2 1 0
NOTE: The Format Track command in Table 5-6 is no longer recommended. The command is supported to guarantee backward compatibility. This command writes the desired head and cylinder of the selected drive with an FFh pattern. To remain host backward compatible, the CompactFlash Memory Card expects a sector buffer of data from the host to follow the command with the same protocol as the Write Sector(s) command although the information in the buffer is not used by the CompactFlash Card. If LBA=1 then the number of sectors to format is taken from the Sec Cnt register (0=256).
5.1.5. Identify Drive--ECH Table 5-7. Identify Drive
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X X X Drive X X X X X 7 6 5 4 ECH X 3 2 1 0
The Identify Drive command enables the host to receive parameter information from the CompactFlash Memory Card. This command has the same protocol as the Read Sector(s) command. The parameter words in the buffer have the arrangement and meanings defined in Table 5-8. All reserved bits or words are zero. Table 5-8 is the definition for each field in the Identify Drive Information. Table 5-8. Identify Drive Information
Word Address Default Value 0 1 2 848Ah XXXXh 0000h Total Bytes 2 2 2 Data Field Type Information General configuration bit-significant information Default number of cylinders Reserved
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Word Address Default Value 3 4 5 6 7-8 9 10-19 20 21 22 23-26 27-46 47 48 49 50 51 52 53 54 55 56 57-58 59 60-61 62 63 64 65 66 67 68 69-79 80 81 82 XXXXh 0000h 0240h XXXXh XXXXh 0000h aaaa 0002h 0002h 0004h aaaa aaaa 000Xh 0000h 0300h 0000h 0200h 0000h 0003h XXXXh XXXXh XXXXh XXXXh 010Xh XXXXh 0000h 0X07h 0003h 0078h 0078h 0078h 0078h 0000h 00XXh 0000h XXXXh
Total Bytes 2 2 2 2 4 2 20 2 2 2 8 40 2 2 2 2 2 2 2 2 2 2 4 2 4 2 2 2 2 Default number of heads
Data Field Type Information
Number of unformatted bytes per track Number of unformatted bytes per sector Default number of sectors per track Number of sectors per card (Word 7 = MSW, Word 8 = LSW) Reserved Serial number in ASCII (Right Justified) Buffer type (dual ported) Buffer size in 512 byte increments Number of ECC bytes passed on Read/Write Long Commands Firmware revision in ASCII (Rev M.ms) set by code Big Endian Byte Order in Word Model number in ASCII (Left Justified) Big Endian Byte Order in Word Maximum of 1 sector on Read/Write Multiple command Double-word not supported Capabilities: DMA Supported (bit 8), LBA supported (bit 9) Reserved PIO data transfer cycle timing mode Single word DMA data transfer cycle timing mode (not supported) Field validity Current number of cylinders Current number of heads Current sectors per track Current capacity in sectors (LBAs) (Word 57 = LSW, Word 58 = MSW) Multiple sector setting is valid Total number of sectors addressable in LBA Mode Single word DMA transfer (not supported) 0-7: Multiword DMA modes supported. 15-8 Multiword DMA mode active Advanced PIO modes supported Minimum multiword DMA transfer cycle time per word in ns Recommended multiword DMA transfer cycle time per word in ns
2 2 20 2 2 2
Minimum PIO transfer without flow control Minimum PIO transfer with IORDY flow control Reserved Major ATA version Minor ATA version Features/command sets supported
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Word Address Default Value 83 84 85 86 87 88 89 90 91 92-127 128-159 160 161 162 163 164 165-175 176-255 X00Xh X0X0h 0000h 000Xh X000h 0000h XXXXh XXXXh XXXXh 0000h 0000h XXXXh 0000h 0000h 0082h 001Bh 0000h 0000h
Total Bytes 2 2 2 2 2 2 2 2 2 72 64 2 2 2 2 2 22 140
Data Field Type Information Features/command sets supported Features/command sets supported Features/command sets enabled Features/command sets enabled Features/command sets enabled Ultra DMA Mode supported and selected Time required for Security erase unit completion Time required for Enhanced security erase unit completion Current Advanced power management value Reserved Reserved vendor-unique bytes Power requirement description Reserved for assignment by the CFA Key management schemes supported CF Advanced True IDE Timing Mode Capability and Setting CF Advanced PCMCIA I/O and Memory Timing Mode Capability Reserved for assignment by the CFA Reserved
5.1.5.1. Word 0: General Configuration This field informs the host that this is a non-magnetic, hard sectored, removable storage device with a transfer rate greater than 10 Mb/sec and is not MFM encoded. CompactFlash products report 848AH in compliance with the CFA specification. 5.1.5.2. Word 1: Default Number of Cylinders This field contains the number of translated cylinders in the default translation mode. This value will be the same as the number of cylinders. 5.1.5.3. Word 3: Default Number of Heads This field contains the number of translated heads in the default translation mode. 5.1.5.4. Word 4: Number of Unformatted Bytes per Track This field contains the number of unformatted bytes per translated track in the default translation mode.
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5.1.5.5. Word 5: Number of Unformatted Bytes per Sector This field contains the number of unformatted bytes per sector in the default translation mode. 5.1.5.6. Word 6: Default Number of Sectors per Track This field contains the number of sectors per track in the default translation mode. 5.1.5.7. Words 7-8: Number of Sectors per Card This field contains the number of sectors per CompactFlash Memory Card. This double word value is also the first invalid address in LBA translation mode. 5.1.5.8. Words 10-19: Memory Card Serial Number The contents of this field are right justified and padded with spaces (20h). 5.1.5.9. Word 20: Buffer Type This field defines the buffer capability with the 0002h meaning a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and the CompactFlash Memory Card. 5.1.5.10. Word 21: Buffer Size This field defines the buffer capacity of 2 sectors or 1 kilobyte of SRAM. 5.1.5.11. Word 22: ECC Count This field defines the number of ECC bytes used on each sector in the Read and Write Long commands. 5.1.5.12. Words 23-26: Firmware Revision This field contains the revision of the firmware for this product. 5.1.5.13. Words 27-46: Model Number This field contains the model number for this product and is left justified and padded with spaces (20h).
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5.1.5.14. Word 47: Read/Write Multiple Sector Count This field contains the maximum number of sectors that can be read or written per interrupt using the Read Multiple or Write Multiple commands. 5.1.5.15. Word 48: Double Word Support This field indicates this product will not support double word transfers. 5.1.5.16. Word 49: Capabilities This field indicates this product will not support DMA data transfers but does support LBA mode. 5.1.5.17. Word 51: PIO Data Transfer Cycle Timing Mode This field defines the mode for PIO data transfer. 5.1.5.18. Word 52: Single Word DMA Data Transfer Cycle Timing Mode This field states this product does not support any Single Word DMA data transfer mode. 5.1.5.19. Word 53: Translation Parameters Valid Bit 0 of this field is set, indicating that words 54 to 58 are valid and reflect the current number of cylinders, heads and sectors. Bit 1 is also set, indicating values in words 64 through 70 are valid. 5.1.5.20. Words 54-56: Current Number of Cylinders, Heads, Sectors/Track These fields contain the current number of user addressable cylinders, heads, and sectors/track in the current translation mode. 5.1.5.21. Words 57- 58: Current Capacity This field contains the product of the current cylinders times heads times sectors. 5.1.5.22. Word 59: Multiple Sector Setting This field contains a validity flag in the odd byte and the current number of sectors that can be transferred per interrupt for R/W Multiple in the even byte. The odd byte is always 01H, which indicates that the even byte is always valid.
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ATA Command Description
The even byte value depends on the value set by the Set Multiple command. The even byte of this word by default contains a 00H, which indicates that R/W Multiple commands are not valid. The only other value returned by the CompactFlash Memory Card in the even byte is a 01H value, which indicates that 1 sector per interrupt, can be transferred in R/W Multiple mode. 5.1.5.23. Words 60-61: Total Sectors Addressable in LBA Mode This field contains the number of sectors addressable for the CompactFlash Card in LBA mode only. 5.1.5.24. Word 64: Advanced PIO Transfer Modes Supported Bits 0 and 1 of this field are set to indicate support for PIO transfer modes 3 and 4, respectively. 5.1.5.25. Word 67: Minimum PIO Transfer Cycle Time Without Flow Control This field indicates in nanoseconds, the minimum cycle time that, if used by the host, the CompactFlash Card guarantees data integrity during the cycle without utilization of flow control. 5.1.5.26. Word 68: Minimum PIO Transfer Cycle Time With Flow Control This field indicates in nanoseconds, the minimum cycle time the CompactFlash Memory Card supports while performing data transfers using flow control. 5.1.5.27. Words 82-84: Features/Command Sets Supported Words 82, 83, and 84 indicate the features and command sets supported. The value 0000h or FFFFh was placed in each of these words by CompactFlash cards prior to ATA-3 and will be interpreted by the host as meaning that features/command sets supported are not indicated. Bits 1 through 13 of Word 83, and bits 0 through 13 of Word 84 are reserved. Bit 14 of Word 83 and Word 84 will be set to "1," and bit 15 of Word 83 and Word 84 will be cleared to zero which indicates that the features and command sets supported words are valid. The values in these words should not be depended on by host implementers.
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ATA Command Description
Table 5-9. Word 82 Description
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Setting 0 1 0 1 0 1 1 0 0 0 0 --1 1 1 --SMART feature set not supported Security Mode feature set supported Removable Media feature set not supported Power Management feature set supported Packet Command feature set not supported Write cache supported Look-ahead supported Release Interrupt not supported Service Interrupt not supported Device Reset command not supported Host Protected Area feature set not supported Obsolete Write Buffer command supported by CF Card Read Buffer command supported by CF Card NOP command supported by CF Card Obsolete Indication
Table 5-10 Word 83 Description
Bit 0 1 2 3 4 Setting 0 0 1 1 0 Indication Download Microcode command not supported by CF Card Read DMA Queued and Write DMA Queued commands not supported by CF Card CFA feature set supported by CF Card Advanced Power Management feature set supported by CF Card Removable Media Status feature set not supported by CF Card
5.1.5.28. Words 85-87: Features/Command Sets Enabled Words 85, 86, and 87 indicates features/command sets enabled. The value 0000h or FFFFh was placed in each of these words by CompactFlash cards prior to ATA-4 and will be interpreted by the host as meaning that features/command sets enabled are not indicated. Bits 1 through 15 of word 86 are reserved. Bits 0-13 of word 87 are reserved. Bit 14 of word 87 will be set to one and bit 15 of word 87 will be cleared to zero to provide indication that the features/command sets enabled words are valid. The values in these words should not be depended upon by host implementers.
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ATA Command Description
Table 5-11. Word 85 Description
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Setting 0 1 0 1 0 1 1 0 0 0 0 --1 1 1 --SMART feature set not enabled Security Mode feature set enabled via the Security Set Password command Removable Media feature set not supported Power Management feature set supported Packet Command feature set not enabled Write cache enabled Look-ahead enabled Release interrupt not enabled Service Interrupt not enabled Device Reset command not supported Host Protected Area feature set not supported Obsolete Write Buffer command supported by CF Card Read Buffer command supported by CF Card NOP command supported by CF Card Obsolete Indication
Table 5-12. Word 86 Description
Bit 0 1 2 3 4 Setting 0 0 1 1 0 Indication Download Microcode command not supported by CF Card Read DMA Queued and Write DMA Queued commands not supported by CF Card CFA feature set supported by CF Card Advanced Power Management feature set enabled via Set Features command Removable Media Status feature set not supported by CF Card
5.1.6. Idle--97H, E3H Table 5-13. Idle
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 E3H or 97H Drive X X X Timer Count (5 msec increments) X X 3 2 1 0
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ATA Command Description
This command causes the CompactFlash Card to set BSY, enter the Idle (Read) mode, clear BSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milliseconds and the automatic power down mode is enabled. If the sector count is zero, the automatic power down mode is disabled. Note that this time base (5 msec) is different from the ATA specification. 5.1.7. Idle Immediate--95H, E1H Table 5-14. Idle Immediate
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 E1H or 95H Drive X X X X X X 3 2 1 0
This command causes the CompactFlash Memory Card to set BSY, enter the Idle (Read) mode, clear BSY and generate an interrupt. 5.1.8. Initialize Drive Parameters--91H Table 5-15. Initialize Drive Parameters
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 0 X Drive X X X Number of Sectors X 7 6 5 4 91H Max Head (no. of heads-1) 3 2 1 0
This command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the Sector Count and the Card/Drive/Head registers are used by this command. NOTE: SanDisk recommends NOT using this command in any system because DOS determines the offset to the Boot Record based on the number of heads and sectors per track. If a CompactFlash Memory Card is "Formatted" with one head and sector per track value, the same CompactFlash Card will not operate correctly with DOS configured with another heads and sectors per track value.
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ATA Command Description
5.1.9. Read Buffer--E4H Table 5-16. Read Buffer
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 E4H X 3 2 1 0
The Read Buffer command enables the host to read the current contents of the CompactFlash Memory Card's sector buffer. This command has the same protocol as the Read Sector(s) command. 5.1.10. Read Multiple--C4H Table 5-17. Read Multiple
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 C4H Head (LBA 27-24) 3 2 1 0
NOTE: The current revision of the CompactFlash Memory Card only supports a block count of 1 as indicated in the Identify Drive Information command. This command is provided for compatibility with future products that may support a larger block count. The Read Multiple command performs similarly to the Read Sectors command. Interrupts are not generated on every sector, but on the transfer of a block, which contains the number of sectors defined by a Set Multiple, command. Command execution is identical to the Read Sectors operation except that the number of sectors defined by a Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Read Multiple command. When the Read Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = (sector count)--modulo (block count).
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ATA Command Description
If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read Multiple commands are disabled, the Read Multiple operation is rejected with an Aborted Command error. Disk errors encountered during Read Multiple commands are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer will take place as it normally would, including transfer of corrupted data, if any. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same as that on a Read Sector(s) Command. This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block that contained the error. 5.1.11. Read Long Sector--22H, 23H Table 5-18. Read Long Sector
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 22H or 23H Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) X X Head (LBA 27-24) 3 2 1 0
The Read Long command performs similarly to the Read Sector(s) command except that it returns 516 bytes of data instead of 512 bytes. During a Read Long command, the CompactFlash Memory Card does not check the ECC bytes to determine if there has been a data error. Only single sector read long operations are supported. The transfer consists of 512 bytes of data transferred in word mode followed by 4 bytes of random data transferred in byte mode. Random data is returned instead of ECC bytes because of the nature of the ECC system used. This command has the same protocol as the Read Sector(s) command.
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ATA Command Description
5.1.12. Read Sector(s)--20H, 21H Table 5-19. Read Sectors
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 20H or 21H Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X Head (LBA 27-24) 3 2 1 0
This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is issued and after each sector of data (except the last one) has been read by the host, the CompactFlash Memory Card sets BSY, puts the sector of data in the buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512 bytes of data from the buffer. At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head, and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. 5.1.13. Read Verify Sector(s)--40H, 41H Table 5-20. Read Verify Sectors
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 40H or 41H Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X Head (LBA 27-24) 3 2 1 0
This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host. When the command is accepted, the CompactFlash Memory Card sets BSY. When the requested sectors have been verified, the CompactFlash Memory Card clears BSY and generates an interrupt. Upon command completion, the Command Block Registers contain the cylinder, head, and sector number of the last sector verified. If an error occurs, the verify terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The Sector Count Register contains the number of sectors not yet verified.
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ATA Command Description
5.1.14. Recalibrate--1XH Table 5-21. Recalibrate
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive X X X X X 7 6 5 4 1XH X 3 2 1 0
This command is effectively a NOP command to the CompactFlash Memory Card and is provided for compatibility purposes. After this command is executed the Cyl High and Cyl Low as well as the Head number will be 0 and Sec Num will be 1 if LBA=0 and 0 if LBA=1 (i.e., the first block in LBA is 0 while CHS mode the sector number starts at 1). 5.1.15. Request Sense--03H Table 5-22. Request Sense
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 X 1 Drive X X X X X 7 6 5 4 03H X 3 2 1 0
This command requests an extended error code after a command ends with an error. Table 5- defines the valid extended error codes for the CompactFlash Memory Card Series product. The extended error code is returned to the host in the Error Register. This command must be the next command issued to the CompactFlash Card following the command that returned an error.
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ATA Command Description
Table 5-23. Extended Error Codes
Extended Error Code 00h 01h 09h 20h 21h 2Fh 35h, 36h 11h 18h 05h, 30-34h, 37h, 3Eh 10h, 14h 3Ah 1Fh No Error Detected Self Test OK (No Error) Miscellaneous Error Invalid Command Invalid Address (Requested Head or Sector Invalid) Address Overflow (Address Too Large) Supply or generated Voltage Out of Tolerance Uncorrectable ECC Error Corrected ECC Error Self Test or Diagnostic Failed ID Not Found Spare Sectors Exhausted Data Transfer Error/Aborted Command Description
0Ch, 38H, 3Bh, 3Ch, 3Fh Corrupted Media Format 03h Write/Erase Failed
5.1.16. Seek--7XH Table 5-24. Seek
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) X (LBA 7-0) X X 7 6 5 4 7XH Head (LBA 27-24) 3 2 1 0
This command is effectively a NOP command to the CompactFlash Memory Card although it does perform a range check of cylinder and head or LBA address and returns an error if the address is out of range.
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ATA Command Description
5.1.17. Set Features--EFH Table 5-25. Set Features
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X Config Feature 7 6 5 4 EFH X 3 2 1 0
This command is used by the host to establish or select certain features. Table 5- defines all features that are supported. Please note that the 9AH feature is unique to the CompactFlash Memory Card and are not part of the ATA Specification. Table 5-26. Features Supported
Feature 01H 03H 55H 66H 69H 81H 96H 9AH BBH CCH Enable 8-bit data transfer. Set Transfer Mode based on value and Sector Count register. Disable Read Look Ahead. Disable Power on Reset (POR) establishment of defaults at Soft Reset. Accepted for backward compatibility with the SDP Series but has no impact on the CF Memory Card. Disable 8-bit data transfer. Accepted for backward compatibility with the SDP Series but has no impact on the CF Memory Card. Accepted for backward compatibility with the SDP Series but has no impact on the CF Memory Card. 4 bytes of data apply on Read/Write Long commands. Enable Power on Reset (POR) establishment of defaults at Soft Reset. Operation
Features 01H and 81H are used to enable and clear 8 bit data transfer mode. If the 01H feature command is issued, all data transfers will occur on the low order D7-D0 data bus and the IOIS16 signal will not be asserted for data register accesses. A host can choose the transfer mechanism by Set Transfer Mode and specifying a value in the Sector Count register. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value.
PIO Default Transfer Mode PIO Flow Control Transfer Mode x Multiword DMA Mode x Reserved Reserved 00000 00d 00001 nnn 00100 nnn 01000 nnn 10000 nnn
Where "nnn" is a valid mode number in binary, "x" is the mode number in decimal for the associated transfer type, and "d" is ignored. Features 55H and BBH are the default features for the CompactFlash Memory Card; thus, the host does not have to issue this command with these features unless it is necessary for compatibility reasons.
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ATA Command Description
The 9AH Feature is accepted for backward compatibility with the SDP Series but has no impact on the CompactFlash Memory Card. SanDisk does not recommend the use of this command in new designs. Features 66H and CCH can be used to enable and disable whether the Power On Reset (POR) Defaults will be set when a soft reset occurs. The default setting is to revert to the POR defaults when a soft reset occurs. POR defaults the number of heads and sectors along with 16 bit data transfers and the read/write multiple block count. 5.1.18. Set Multiple Mode--C6H Table 5-27. Seat Multiple Mode
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X Sector Count X 7 6 5 4 C6H X 3 2 1 0
This command enables the CompactFlash Card to perform Read and Write Multiple operations and establishes the block count for these commands. The Sector Count Register is loaded with the number of sectors per block. The current version of the CompactFlash Card supports only a block size of 1 sector per block. Future versions may support larger block sizes. Upon receipt of the command, the CompactFlash Card sets BSY to 1 and checks the Sector Count Register. If the Sector Count Register contains a valid value and the block count is supported, the value is loaded for all subsequent Read Multiple and Write Multiple commands and execution of those commands is enabled. If a block count is not supported, an Aborted Command error is posted, and Read Multiple and Write Multiple commands are disabled. If the Sector Count Register contains 0 when the command is issued, Read and Write Multiple commands are disabled. At power on, or after a hardware or (unless disabled by a Set Feature command) software reset, the default mode is Read and Write Multiple disabled. 5.1.19. Set Sleep Mode- 99H, E6H Table 5-28. Set Sleep Mode
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 E6H or 99H Drive X X X X X X 3 2 1 0
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ATA Command Description
This command causes the CompactFlash Memory Card to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply issuing another command (a reset is permitted but not required). Sleep mode is also entered when internal timers expire so the host does not need to issue this command except when it wishes to enter Sleep mode immediately. The default value for the read to sleep timer is 5 milliseconds. Note that this time base (5 msec) is different from the ATA Specification. 5.1.20. Standby--96H, E2H Table 5-29. Standby
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 E2H or 96H Drive X X X X X X 3 2 1 0
This command causes the CompactFlash Memory Card to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required). 5.1.21. Standby Immediate--94H, E0H Table 5-30. Standby Immediate
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 E0H or 94H Drive X X X X X X 3 2 1 0
This command causes the CompactFlash Memory Card to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required).
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ATA Command Description
5.1.22. Translate Sector--87H Table 5-31. Translate Sector
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) X X 7 6 5 4 87H Head (LBA 27-24) 3 2 1 0
When this command is issued, the controller responds with a 512-byte buffer of information on the desired cylinder, head and sector with the actual Logical Address. Table 5- represents the information in the buffer. Please note that this command is unique to the SanDisk CompactFlash Memory Card. Table 5-32. Translate Sector Information
Address 00 01-02 03 04-07 08 09-0A 0B 0C-1FF Information Head Cylinder Sector LBA Chip Block Page Reserved
5.1.23. Wear Level--F5H Table 5-33. Wear Level
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X X X Drive X X X Completion Status X 7 6 5 4 F5H Flag 3 2 1 0
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ATA Command Description
This command is effectively a NOP command and only implemented for backward compatibility with earlier SanDisk SDP series products. The Sector Count Register will always be returned with an 00H indicating Wear Level is not needed. 5.1.24. Write Buffer--E8H Table 5-34. Write Buffer
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 E8H X 3 2 1 0
The Write Buffer command enables the host to overwrite contents of the CompactFlash Memory Card's sector buffer with any data pattern desired. This command has the same protocol as the Write Sector(s) command and transfers 512 bytes. 5.1.25. Write Long Sector--32H, 33H Table 5-35. Write Long Sector
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 32H or 33H Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) X X Head (LBA 27-24) 3 2 1 0
This command is provided for compatibility purposes and is similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes. Only single sector Write Long operations are supported. The transfer consists of 512 bytes of data transferred in word mode followed by 4 bytes of ECC transferred in byte mode. Because of the unique nature of the solid-state CompactFlash Memory Card, the four bytes of ECC transferred by the host cannot be used by the CompactFlash Card. The CompactFlash Card discards these four bytes and writes the sector with valid ECC fields. This command has the same protocol as the Write Sector(s) command.
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ATA Command Description
5.1.26. Write Multiple Command--C5H Table 5-36. Write Multiple Command
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X LBA X Drive Cylinder High Cylinder Low Sector Number Sector Count X 7 6 5 4 C5H Head 3 2 1 0
NOTE: The current revision of the CompactFlash Memory Card only supports a block count of 1 as indicated in the Identify Drive Command information. This command is provided for compatibility with future products that may support a larger block count. This command is similar to the Write Sectors command. The CompactFlash Memory Card sets BSY within 400 nsec of accepting the command. Interrupts are not presented on each sector but on the transfer of a block that contains the number of sectors defined by Set Multiple. Command execution is identical to the Write Sectors operation except that the number of sectors defined by the Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Write Multiple command. When the Write Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the sector/block, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = remainder (sector count/block count). If the Write Multiple command is attempted before the Set Multiple Mode command has been executed or when Write Multiple commands are disabled, the Write Multiple operation will be rejected with an aborted command error. Errors encountered during Write Multiple commands are posted after the attempted writes of the block or partial block transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred and the Sector Count Register contains the residual number of sectors that need to be transferred for successful completion of the command e.g., each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector. The Sector Count Register contains 6 and the address is that of the third sector.
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ATA Command Description
5.1.27. Write Multiple without Erase--CDH Table 5-37. Write Multiple without Erase
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X LBA X Drive Cylinder High Cylinder Low Sector Number Sector Count X 7 6 5 4 CDH Head 3 2 1 0
SanDisk does not recommend the use of this command in new designs but it is supported as a normal Write Sectors command for backward compatibility reasons. 5.1.28. Write Sector(s)--30H, 31H Table 5-38. Write Sectors
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 30H or 31H Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X Head (LBA 27-24) 3 2 1 0
This command writes from 1 to 256 sectors as specified in the Sector Count Register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is accepted, the CompactFlash Memory Card sets BSY, then sets DRQ and clears BSY, then waits for the host to fill the sector buffer with the data to be written. No interrupt is generated to start the first buffer fill operation. No data should be transferred by the host until BSY has been cleared by the host. For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is cleared. It will remain in this state until the command is completed at which time BSY is cleared and an interrupt is generated. If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector.
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ATA Command Description
5.1.29. Write Sector(s) without Erase--38H Table 5-39. Write Sectors without Erase
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 38H Head (LBA 27-24) 3 2 1 0
SanDisk does not recommend the use of this command in new designs but it is supported as a normal Write Sectors command for backward compatibility reasons. 5.1.30. Write Verify Sector(s)--3CH Table 5-40. Write Verify Sectors
Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 3CH Head (LBA 27-24) 3 2 1 0
This command writes from 1 to 256 sectors as specified in the Sector Count Register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is accepted, the CompactFlash Memory Card sets BSY, then sets DRQ and clears BSY, then waits for the host to fill the sector buffer with the data to be written. No interrupt is generated to start the first buffer fill operation. No data should be transferred by the host until BSY has been cleared by the host. For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is cleared. It will remain in this state until the command is completed at which time BSY is cleared and an interrupt is generated. If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector.
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ATA Command Description
5.2. Error Posting
Table 5- summarizes the valid status and error value for all the ATA Command set. Table 5-41. Error and Status Register
Command BBK Check Power Mode Execute Drive Diagnostic* Erase Sector(s) Format Track Identify Drive Idle Idle Immediate Initialize Drive Parameters Read Buffer Read Multiple Read Long Sector Read Sector(s) Read Verify Sectors Recalibrate Request Sense Seek Set Features Set Multiple Mode Set Sleep Mode Stand By Stand By Immediate Translate Sector Wear Level Write Buffer Write Long Sector Write Multiple Write Multiple w/o Erase Write Sector(s) Write Sector(s) w/o Erase Write Verify Sector(s) Invalid Command Code V = valid on this command * See Table 5-2. V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V UNC Error Register IDNF ABRT V AMNF DRDY V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Status Register DWF V DSC V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V CORR ERR V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
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6. CIS Description
This section describes the Card Information Structure (CIS) for the CompactFlash Memory Card. Table 6-1. Card Information Structure
Attribute Offset 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh Data 01h 03h D9 12h FFh 1Ch 05h 03h Reserved 0 Dev ID Type Dh = I/O #address unit-1 = 1 unit W 1 3 0 Speed 1h = 250 ns W 1 Dev ID Type Dh = I/O #address unit-1 = 3 units W 3 Speed 1h =250ns Size Code = 8K units 7 6 5 4 3 2 1 0 xDescription of Contents Device Info Tuple Link is 3 bytes I/O Device, No WPS, speed=250ns if no wait (3) 8-KB of address space End of device info field Other Conditions Info Tuple Link is 5 bytes Conditions: 3V operation is allowed, and WAIT is used I/O Device, No WPS, speed = 250 ns if no wait (One) 2Kilobytes of address space End of device info field Note used JEDEC ID Common Mem Link is 2 bytes PCMCIA JEDEC Manufacturer's ID PCMCIA Code for PC Card-ATA No Vpp Required CISTPL_MANFID First Byte of JEDEC ID for SanDisk PC Card-ATA 12V Second Byte of JEDEC ID CIS Function Tuple Code Link to next Tuple Device ID, WPS, Speed Device Size End Marker Tuple Code Link to next tuple 3 Volts Operation, Wait Function
CISTPL_DEVICE
List End Marker CISTPL_DEVICE_OC
010h
D9h
Device ID, WPS, Speed
012h 014h 016h 018h 01Ah 01Ch 01Eh
01h FFh 00h 18h 02h DFh 01h
Size Code = 2K units
Device Size End Marker Not Used Tuple Code Link Length Byte 1, JEDEC ID of Device 1 (0-2K) Byte 2, JEDEC ID
List End Marker Not Used CISTPL_JEDEC_C
020h 022h 024h 026h 028h 02Ah
20h 04h 45h 00h 01h 04h
Manufacturer's ID Tuple Link is 4 bytes
Tuple Code Link Length Low Byte of PCMCIA Mfg ID High Byte of PCMCIA Mfg ID Low Byte Product Code High Byte Product Code
Low Byte of PCMCIA Manufacturer's Code High Byte of PCMCIA Manufacturer's Code Low Byte of Product Code High Byte of Product Code
SanDisk JEDEC Manufacturer's ID Code of 0 because other byte is JEDEC 1 byte Manufacturer's ID SanDisk Code for SDP Series SanDisk Code for PC Card ATA
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CIS Description
Attribute Offset 02Ch 02Eh 030h 032h 034h 036h 038h 03Ah 03Ch 03Eh 040h 042h 044h 046h 048h 04Ah 04Ch 04Eh 050h 052h 054h 056h 058h 05Ah 05Ch 05Eh 060h
Data 15h 17h 04h 01h 53h 61h 6Eh 44h 69h 73h 6Bh 00h 53h 44h 50h 00h 35h 2Fh 33h 20h 30h 2Eh 36h 00h FFh 80h 03h
7
6
5
4
3
2
1
0
Description of Contents Level 1 version/product info Link to next tuple is 23 bytes
CIS Function Tuple Code Link Length Major Version Minor Version String 1
CISTPL_VER_1
TPPLV1_MAJOR TPPLV1_MINOR ASCII Manufacturer String
PCMCIA 2.0/JEIDA 4.1 PCMCIA 2.0/JEIDA 4.1 'S' 'a'1 'n' 'D' 'i' 's' 'k'
End of Manufacturer String ASCII Product Name String
Null terminator 'S' 'D' 'P' Info String 2
End of Product Name String
Null terminator '5' '/' '3' '' Info String 3
SanDisk Card CIS Revision Number
'0' '.' '6'
End of CIS Revision Number End of List Marker CISTPL_VEND_SPECIF_80 (Field Bytes 3-4 taken as 0)
Null terminator FFh List terminator SanDisk Parameters Tuple Link length is 3 byte No Info String 4 Tuple Code Link to next tuple and length of info in this tuple
1
Legacy CompactFlash products may report "SunDisk" as the ASCII manufacture string.
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CIS Description
Attribute Offset 062h
Data 14h
7 W
6 12
5
4
3 P D N A 0
2 R I A 1
1 R I R 0
0 SP
Description of Contents No Wear Level & NO Vpp W:No Wear Level 12:Vpp Not used on Write NI:-INPACK connected PP:Programmable Power PDNA:Pwr Down Not Abort--Cmd RIA:RBsy, ATBsy connected RIR:RBsy Inhibited at Reset SP:No Security Present This definition applies only to cards with Manufacturer's ID tuple 1st 3 bytes 45 00 01. R8:8 bit ROM present TAR:Temp Bsy on AT Reset TPR:Temp Bsy on PCMCIA -- Reset E:Erase Ahead Available R:Reserved, 0 for now This definition applies only to card with Manufacturer's ID tuple 1st 3 bytes 45 00 01.
CIS Function SanDisk Fields, 1 to 4 bytes limited by link length.
NI PP
0
0
0
1
0
064h
08h
R
R
R
R
E
T P R 0
T A R 0
R8
0
0
0
0
1
0
SanDisk Fields, 1 to 4 bytes limited by link length.
066h 068h 06Ah 06Ch 06Eh
00h 21h 02h 04h 01h R 0 R 0 Function Type Code R 0 R 0 R 0 R 0 R 0 P 1 CISTPL_FUNCID Function ID Tuple Link length is 2 bytes Disk Function Attempt installation at Post P:Install at POST R:Reserved(0) Function Extension Tuple Link length is 2 bytes Disk Function Extension Tuple Type Interface Type Code CISTPL_FUNCE Extension tuple describes the Interface Protocol PC Card-ATA Interface Function Extension tuple This tuple has 3 info bytes Disk Function Extension Tuple Type R 0 Basic PCMCIA-ATA Extension tuple R 0
For Specific platform use Only Tuple Code Link to next tuple Function Code
070h 072h 074h 076h 078h 07Ah 07Ch 07Eh
22h 02h 01h 01h 22h 03h 02h 0Ch
CISTPL_FUNCE
Tuple Code Link to next tuple Extension Tuple Type for Disk Extension Info Tuple Code Link Length Extension Tuple Type for Disk R 0
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CIS Description
Attribute Offset 07Eh
Data 0Ch
7 R 0
6 R 0
5 R 0
4 R 0
3 U 1
2 S 1
1 V 0
0
Description of Contents No Vpp, Silicon Drive with Unique Manufacturer/Serial Number combined string V=0:No Vpp Required V=1:Vpp on Modify Media V=2:Vpp on any operation V=3:Vpp continuous S:Silicon, else Rotating U:ID Drive Mfg/SN Unique All power down modes and power commands are not needed to minimize power. P0:Sleep Mode Supported P1:Standby Mode Supported P2:Idle Mode Supported P3:Drive Auto Power Control N:Some Config Excludes 3X7 E:Index Bit is Emulated I:Twin -IOis16 Data Reg Only Configuration Tuple Link Length is 5 bytes
CIS Function Basic ATA Option Parameters
080h
0Fh
R 0
I 0
E 0
N 0
P3 P2 P1 P0 1 1 1 1
Extended ATA Option Parameters
082h 084h 086h
1Ah 05h 01h RFS 00
CISTPL_CONF
Tuple Code Link to next tuple Size of fields byte (TPCC_SZ)
RMS 00
RAS 01
Size of Reserved Field is 0 bytes, Size of Register Mask is 1 Byte, Size of Config Base Address is 2 bytes RFS:Bytes in Reserved Field RMS:Bytes in Reg Mask-1 RAS:Bytes in Base Addr-1 Entry with Config Index of 07h is final entry in table Configuration Registers are located at 200h in Reg Space.
088h 08Ah 08Ch 08Eh
07h 00h 02h 0Fh R 0 R 0
TPCC_LAST TPCC_RADR (lsb) TPCC_RADR (msb) R 0 R 0 S 1 P 1 C 1 I 1
Last entry of configuration table Location of Config Registers TPCC_RMSK
First 4 Configuration Registers are present I:Configuration Index C:Configuration and Status P:Pin Replacement S:Socket and Copy R:Reserved for future use Configuration Entry Tuple Link to next tuple is 11 bytes. Also limits size of this tuple to 13 bytes.
090h 092h
1Bh 0Bh
CISTPL_CE
Tuple Code Link to next tuple
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CIS Description
Attribute Offset 094h
Data C0h
7 I 1
6 D 1
5
4
3
2
1
0
Description of Contents Memory Mapped I/O Configuration Configuration Index for this entry is 0. Interface Byte follows this byte. Default Configuration, so is not dependent on previous Default Configuration. D:Default Configuration I:Interface Byte Follows Memory Only Interface(0), Bvd's and wProt not used, Ready/-Busy and Wait for memory cycles active. B:Battery Volt Detects Used P:Write Protect Used R:Ready/-Busy Used W:Wait Used for Memory Cycles Vcc only Power; No Timing, I/O, or IRQ; 2 Byte Mem Space Length; Misc Entry Present P:Power info type T:Timing info present IO:I/O port info present IR:Interrupt info present MS:Mem space info type M:Misc info byte(s) present Nominal Voltage Follows NV:Nominal Voltage LV:Mimimum Voltage HB:Maximum Voltage SI:Static Current AI:Average Current PI:Peak Current DI:Power Down Current Vcc Nominal is 5 Volts Vcc Nominal is 4.5 Volts Vcc Nominal is 5.5 Volts Max Average Current over 10 msec is 80 mA Length of Mem Space is 2 KB Start at 0 on card
CIS Function TPCE_INDX
Configuration Index 0
096h
C0h
W 1
R 1
P 0
B 0
Interface Type 0
TPCE_IF
098h
A1h
M 1
MS 1
IR 0
IO 0
T 0
P 1
TPCE_FS
09Ah
27h
R 0
DI 0
PI 1
AI 0
SI HV LV NV 0 1 1 1
Power Parameters for Vcc
09Ch 09Eh 0A0h 0A2h 0A4h 0A6h
55h 4Dh 5Dh 75h 08h 00h
X 0 X 0 X 0 X 0
Mantissa Ah = 5.0 Mantissa 9h = 4.5 Mantissa Bh = 5.5 Mantissa Eh = 8.0
Exponent 5h = 1V Exponent 5h = 1V Exponent 5h = 1V Exponent 5h = 10
Vcc Nominal Value Vcc Minimum Value Vcc Maximum Value Max Average Current TPCE_MS Length LSB TPCE_MS Length MSB
Length in 256 bytes pages (lsb) Length in 256 bytes pages (msb)
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CIS Description
Attribute Offset 0A8h
Data 21h
7 X 0
6 R 0
5 P 1
4 RO 0
3 A 0
2
1 T 1
0
Description of Contents Power-Down, and Twin Card. T:Twin Cards Allowed A:Audio Supported RO:Read Only Mode P:Power Down Supported R:Reserved X:More Misc Fields Bytes Configuration Entry Tuple Link to next tuple is 6 bytes. Also limits size of this tuple to 8 bytes.
CIS Function TPCE_MI
0AAh 0ACh 0AEh
1Bh 06h 00h I 0 D 0 MS 0 DI 0 PI 1
CISTPL_CE
Tuple Code Link to next tuple TPCE_INDX
Configuration Index 0 IR 0 AI 0 IO 0 SI 0 T 0 H 0 P 1 LV NV 0 1
Memory mapped I/O 3.3V configuration. P:Power info type
0B0h
01h
M 0
TPCE_FS
0B2h
21h
R 0
PI:Peak Current NV:Nominal Operation Supply Voltage Nominal Operation Supply Voltage = 3.0V +.30
TPCE_PD
0B4h 0B6h 0B8h 0BAh 0BCh 0BEh
B5h 1Eh 4Dh 1Bh 0Dh C1h
X 1 X 0 X 0
Mantissa 6h = 3.0 1Eh Mantissa 9h = 4.5 CISTPL_CE
Exponent 5h = 1
Nominal Operation Supply Voltage Nominal Operation Supply Voltage Extension Byte Max Average Current Tuple Code Link to next tuple TPCE_INDX
Exponent 5h = 10
Max Average Current over 10 msec is 45mA Configuration Entry Tuple Link to next tuple is 13 bytes. Also limits size of this tuple to 15 bytes.
I 1
D 1
Configuration Index 1
I/O Mapped Contiguous 16 registers configuration Configuration Index for this entry is 1. Interface Byte follows this byte. Default Configuration, so is not dependent on previous Default Configuration. D:Default Configuration I:Interface Byte Follows I/O Interface(1), Bvd's and wProt not used; Ready/-Busy active but Wait not used for memory cycles. B:Battery Volt Detects Used P:Write Protect Used R:Ready/-Busy Used W:Wait Used for Memory Cycles
0C0h
41h
W 0
R 1
P 0
B 0
Interface Type 1
TPCE_IF
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CIS Description
Attribute Offset 0C2h
Data 99h
7
6
5
4 IO 1
3
2 T 0
1
0
Description of Contents P 1
CIS Function Vcc Only Power Descriptors; No Timing; I/O and IRQ present; No Mem Space; Misc Entry Present P:Power info type T:Timing info present IO:I/O port info present IR:Interrupt info present MS:Mem space info type M:Misc info byte(s) present Power Parameters for Vcc
M MS IR 1 0 1
0C4h
27h
R 0
DI PI 0 1
AI 0
SI HV LV NV 0 1 1 1
Nominal Voltage Follows NV:Nominal Voltage LV:Mimimum Voltage HB:Maximum Voltage SI:Static Current AI:Average Current PI:Peak Current DI:Power Down Current Vcc Nominal is 5Volts Vcc Nominal is 4.5 Volts Vcc Nominal is 5.5Volts Max Average Current over 10 msec is 80 mA Supports both 8 and 16 bit I/O hosts. 4 Address lines and no range so 16 registers and host must do all selection decoding. IO AddrLines:#lines decoded E:Eight bit only hosts supported S:Sixteen bit hosts supported R:Range Follows
0C6h 0C8h 0CAh 0CCh 0CEh
55h 4Dh 5Dh 75h 64h
X 0 X 0 X 0 X 0 R 0 S 1
Mantissa Ah = 5.0 Mantissa 9h = 4.5 Mantissa Bh = 5.5 Mantissa Eh = 8.0 E 1
Exponent 5h = 1V Exponent 5h = 1V Exponent 5h = 1V Exponent 5h = 10 IO AddeLines 4
Vcc Nominal Value Vcc Minimum Value Vcc Maximum Value Max Average Current TPCE_IO
0D0h
F0h
S 1
P 1
L 1
M 1
V 0
B 0
I 0
N 0
IRQ Sharing Logic Active in Card Control & Status Register, Pulse and Level Mode Interrupts supported, Recommended IRQ's any of 0 through 15(F) S:Share Logic Active P:Pulse Mode IRQ Supported L:Level Mode IRQ Supported M:Bit Mask of IRQs Present V:Vendor Unique IRQ B:Bus Error IRQ I:IO Check IRQ N:Non-Maskable IRQ
TPCE_IR
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CIS Description
Attribute Offset 0D2h
Data FFh
7 7 1
6 6 1 E 1 R 0
5 5 1 D 1
4 4 1 C 1
3 3 1 B 1 A 0
2 2 1 A 1
1 1 1 9 1 T 1
0 0 1 8 1
Description of Contents IRQ Levels to be routed 0 - 15 recommended. Recommended routing to any "normal, maskable" IRQ. Power-Down, and Twin Card. T:Twin Cards Allowed A:Audio Supported RO:Read Only Mode P:Power Down Supported R:Reserved X:More Misc Fields Bytes Configuration Entry Tuple Link to next tuple is 6 bytes. Also limits size of this tuple to 8 bytes.
CIS Function TPCE_IR Mask Extension Byte 1 TPCE_IR Mask Extension Byte 2 TPCE_MI
0D4h
FFh
F 1
0D6h
21h
X 0
P RO 1 0
0D8h 0DAh 0DCh
1Bh 06h 01h I 0 D 0 MS 0 DI 0 PI 1
CISTPL_CE
Tuple Code Link to next tuple TPCE_INDX
Configuration Index 1 IR 0 AI 0 IO 0 T 0 P 1
I/O mapped contiguous 16 3.3V configuration P:Power info type
0DEh
01h
M 0
TPCE_FS
0E0h
21h
R 0
SI HV LV NV 0 0 0 1
PI:Peak Current NV:Nominal Operation Supply Voltage Nominal Operation Supply Voltage = 3.0V +.30
Power Parameters for Vcc
0E2h 0E4h 0E6h 0E8h 0EAh 0ECh
B5h 1Eh 4Dh 1Bh 12h C2h
X 1 X 0 X 0
Mantissa 6h = 3.0 1Eh Mantissa 9h = 4.5 CISTPL_CE
Exponent 5h = 1
Nominal Operation Supply Voltage Nominal Operation Supply Voltage Extension Byte Max Average Current Tuple Code Link to next tuple TPCE_INDX
Exponent 5h = 10
Max Average Current over 10 msec is 45 mA Configuration Entry Tuple Link to next tuple is 18 bytes. Also limits size of this tuple to 20 bytes.
I 1
D 1
Configuration Index 2
AT Fixed Disk Primary I/O Address Configuration Configuration Index for this entry is 2. Interface Byte follows this byte. Default Configuration
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CIS Description
Attribute Offset 0EEh
Data 41h
7 W 0
6 R 1
5 P 0
4 B 0
3
2
1
0
Description of Contents I/O Interface(1), Bvd's and wProt not used; Ready/-Busy active but Wait not used for memory cycles. B:Battery Volt Detects Used P:Write Protect Used R:Ready/-Busy Used W:Wait Used for Memory Cycles Vcc Only Power Description; No Timing; I/O and IRQ present; No Mem Space; Misc Entry present P:Power info type T:Timing info present IO:I/O port info present IR:Interrupt info present MS:Mem space info type M:Misc info byte(s) present Nominal Voltage Follows NV:Nominal Voltage LV:Mimimum Voltage HB:Maximum Voltage SI:Static Current AI:Average Current PI:Peak Current DI:Power Down Current Vcc Nominal is 5Volts Vcc Nominal is 4.5Volts Vcc Nominal is 5.5Volts Max Average Current over 10 msec is 80 mA Supports both 8 and 16 bit I/O hosts. 10 Address lines with range so card will respond only to indicated (1F01F7, 3F6-3F7) on A9 through A0 for I/O cycles. IO AddrLines:#lines decoded E:Eight bit only hosts supported S:Sixteen bit hosts supported R:Range Follows
CIS Function TPCE_IF
Interface Type 1
0F0h
99h
M 1
MS 0
IR 1
IO 1
T 0
P 1
TPCE_FS
0F2h
27h
R 0
DI 0
PI 1
AI 0
SI HV LV NV 0 1 1 1
Power Parameters for Vcc
0F4h 0F6h 0F8h 0FAh 0FCh
55h 4Dh 5Dh 75h EAh
X 0 X 0 X 0 X 0 R 1 S 1
Mantissa Ah = 5.0 Mantissa 9h = 4.5 Mantissa Bh = 5.5 Mantissa Eh = 8.0 E 1
Exponent 5h = 1V Exponent 5h = 1V Exponent 5h = 1V Exponent 5h = 10 IO AddeLines Ah = 10
Vcc Nominal Value Vcc Minimum Value Vcc Maximum Value Max Average Current TPCE_IO
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CIS Description
Attribute Offset 0FEh
Data 61h
7 LS 1
6
5 AS 2
4
3
2
1
0
Description of Contents Number of Ranges is 2; Size of each address is 2 bytes; Size of each length is 1 byte. AS:Size of Addresses 0:No Address Present 1:1Byte (8 bit) Addresses 2:2Byte (16 bit) Addresses 3:4Byte (32 bit) Addresses LS:Size of length 0:No Lengths Present 1:1Byte (8 bit) Lengths 2:2Byte (16 bit) Lengths 3:4Byte (32 bit) Lengths First I/O Range base is 1F0h 8 bytes total ==> 1F0-1F7h 2nd I/O Range base is 3F6h 2 bytes total ==> 3F6-3F7h IRQ Sharing Logic Active in Card Control & Status Register, Pulse and Level Mode Interrupts supported, Recommended IRQ's any of 0 through 15(F) S:Share Logic Active P:Pulse Mode IRQ Supported L:Level Mode IRQ Supported M:Bit Mask of IRQs Present M=0 so bits 3-0 are single level, binary encoded Power-Down, and Twin Card. T:Twin Cards Allowed A:Audio Supported RO:Read Only Mode P:Power Down Supported R:Reserved X:More Misc Fields Bytes Configuration Entry Tuple Link to next tuple is 6 bytes. Also limits size of this tuple to 8 bytes.
CIS Function I/O Range Format Description
N Ranges - 1 1
100h 102h 104h 106h 108h 10Ah 10Ch
F0h 01h 07h F6h 03h 01h EEh S 1
1st I/O Base Address (lsb) 1st I/O Base Address (msb) 1st I/O Range Length - 1 2nd I/O Base Address (lsb) 2nd I/O Base Address (msb) 2nd I/O Range Length - 1 P 1 L 1 M 0 Recommend IRQ Level Eh = 14
I/O Length - 1
I/O Length - 1 TPCE_IR
10Eh
21h
X 0
R 0
P 1
RO 0
A 0
T 1
TPCE_MI
110h 112h 114h
1Bh 06h 02h I 0 D 0
CISTPL_CE
Tuple Code Link to next tuple TPCE_INDX
Configuration Index 2
AT Fixed Disk Primary I/O 3.3V configuration
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CIS Description
Attribute Offset 116h
Data 01h
7 M 0
6 MS 0 DI 0
5
4 IR 0
3 IO 0
2 T 0
1 P 1
0
Description of Contents P:Power info type
CIS Function TPCE_FS
118h
21h
R 0
PI 1
AI 0
SI HV LV NV 0 0 0 1
PI:Peak Current NV:Nominal Operation Supply Voltage Nominal Operation Supply Voltage = 3.0V +.30
Power Parameters for Vcc
11Ah 11Ch 11Eh 120h 122h 124h
B5h 1Eh 4Dh 1Bh 12h C3h
X 1 X 0 X 0
Mantissa 6h = 3.0 1Eh Mantissa 9h = 4.5 CISTPL_CE
Exponent 5h = 1
Nominal Operation Supply Voltage Nominal Operation Supply Voltage Extension Byte Max Average Current Tuple Code Link to next tuple TPCE_INDX
Exponent 5h = 10
Max Average Current over 10 msec is 45mA Configuration Entry Tuple Link to next tuple is 18 bytes. Also limits size of this tuple to 20 bytes.
I 1
D 1
Configuration Index 3
AT Fixed Disk Secondary I/O Address Configuration Configuration Index for this entry is 3. Interface Byte follows this byte. Default Configuration I/O Interface(1), Bvd's and wProt not used; Ready/-Busy active but Wait not used for memory cycles. B:Battery Volt Detects Used P:Write Protect Used R:Ready/-Busy Used W:Wait Used for Memory Cycles Vcc Only Power Descriptors; No Timing; I/O and IRQ present; No Mem Space; Misc Entry Present. P:Power info type T:Timing info present IO:I/O port info present IR:Interrupt info present MS:Mem space info type M:Misc info byte(s) present Nominal Voltage Follows NV:Nominal Voltage LV:Mimimum Voltage HB:Maximum Voltage SI:Static Current AI:Average Current PI:Peak Current DI:Power Down Current Vcc Nominal is 5Volts Vcc Nominal is 4.5Volts
126h
41h
W 0
R 1
P 0
B 0
Interface Type 1
TPCE_IF
128h
99h
M 1
MS 0
IR 1
IO 1
T 0
P 1
TPCE_FS
12Ah
27h
R 0
DI 0
PI 1
AI 0
SI HV LV NV 0 1 1 1
Power Parameters for Vcc
12Ch 12Eh
55h 4Dh
X 0 X 0
Mantissa Ah = 5.0 Mantissa 9h = 4.5
Exponent 5h = 1V Exponent 5h = 1V
Vcc Nominal Value Vcc Minimum Value
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CIS Description
Attribute Offset 130h 132h 134h
Data 5Dh 75h EAh
7 X 0 X 0 R 1
6
5
4
3
2
1
0
Description of Contents Vcc Nominal is 5.5Volts Max Average Current over 10 msec is 80 mA Supports both 8 and 16 bit I/O hosts. 10 Address lines with range so card will respond only to indicated (170177, 376-377) on A9 through A0 for I/O cycles. IO AddrLines:#lines decoded E:Eight bit only hosts supported S:Sixteen bit hosts supported R:Range Follows Number of Ranges is 2; Size of each address is 2 bytes; Size of each length is 1 byte. AS:Size of Addresses 0:No Address Present 1:1Byte (8 bit) Addresses 2:2Byte (16 bit) Addresses 3:4Byte (32 bit) Addresses LS:Size of length 0:No Lengths Present 1:1Byte (8 bit) Lengths 2:2Byte (16 bit) Lengths 3:4Byte (32 bit) Lengths First I/O Range base is 170h 8 bytes total ==> 170-177h 2nd I/O Range base is 376h 2 bytes total ==> 376-377h IRQ Sharing Logic Active in Card Control & Status Register, Pulse and Level Mode Interrupts supported, Recommended IRQ's any of 0 through 15(F) S:Share Logic Active P:Pulse Mode IRQ Supported L:Level Mode IRQ Supported M:Bit Mask of IRQs Present M=0 so bits 3-0 are single level, binary encoded
CIS Function Vcc Maximum Value Max Average Current TPCE_IO
Mantissa Bh = 5.5 Mantissa Eh = 1.0 S 1 E 1
Exponent 5h = 1V Exponent 5h = 10 IO AddeLines Ah = 10
136h
61h
LS 1
AS 2
N Ranges-1 1
I/O Range Format Description
138h 13Ah 13Ch 13Eh 140h 142h 144h
70h 01h 07h 76h 03h 01h EEh S 1
1st I/O Base Address (lsb) 1st I/O Base Address (msb) 1st I/O Range Length - 1 2nd I/O Base Address (lsb) 2nd I/O Base Address (msb) 2nd I/O Range Length - 1 P 1 L 1 M 0 Recommend IRQ Level Eh = 14
I/O Length - 1
I/O Length - 1 TPCE_IR
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CIS Description
Attribute Offset 146h
Data 21h
7 X 0
6 R 0
5
4
3 A 0
2
1 T 1
0
Description of Contents Power-Down, and Twin Card. T:Twin Cards Allowed A:Audio Supported RO:Read Only Mode P:Power Down Supported R:Reserved X:More Misc Fields Bytes Configuration Entry Tuple Link to next tuple is 6 bytes. Also limits size of this tuple to 8 bytes.
CIS Function TPCE_MI
P RO 1 0
148h 14Ah 14Ch
1Bh 06h 03h I 0 D 0 MS 0 DI 0 PI 1
CISTPL_CE
Tuple Code Link to next tuple TPCE_INDX
Configuration Index 3 IR 0 AI 0 IO 0 T 0 P 1
AT Fixed Disk Secondary I/O 3.3V configuration P:Power info type
14Eh
01h
M 0
TPCE_FS
150h
21h
R 0
SI HV LV NV 0 0 0 1
PI:Peak Current NV:Nominal Operation Supply Voltage Nominal Operation Supply Voltage = 3.0V Nominal Operation Supply Voltage Extension Byte Max Average Current over 10 msec is 45mA Configuration Entry Tuple Link to next tuple is 4 bytes.
Power Parameters for Vcc
152h 154h 156h 158h 15Ah 15Ch
B5h 1Eh 4Dh 1Bh 04h 07h
X 1 X 0 X 0
Mantissa 6h = 3.0 1Eh Mantissa 9h = 4.5 CISTPL_CE
Exponent 5h = 1 +.30 Exponent 5h = 10
Nominal Operation Supply Voltage
Max Average Current Tuple Code Link to next tuple TPCE_INDX
I 0
D 0 MS 0
Configuration Index 7 IR 0 IO 0 T 0 P 0
AT Fixed Disk Secondary I/O 3.3V configuration P:Power info type
15Eh
00h
M 0
TPCE_FS
160h 162h 164h 166h 168h
028h 0D3h 014h 000h 0FFh CISTPL_NO_LINK No Bytes Following End of Tuple Chain
SanDisk Code SanDisk Code Prevent Scan of Common Memory Link Length is 0 Bytes End of CIS
Reserved Reserved Tuple Code Link to next tuple Tuple Code
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CIS Description
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Appendix A. Ordering Information
To order SanDisk products directly from SanDisk, call 408-542-0595.
Model No. SDCFJ-32-388 SDCFJ-64-388 SDCFJ-128-388 SDCFJ-256-388 SDCFJ-512-388 SDCFJ-1024-388 SDCFJ-2048-388 SDCFJ-4096-388 SDCFH-512-388 SDCFH-1024-388 SDCFH-2048-388 SDCFH-4096-388 SDCFH-4096-3882 SDCFH-8192-388 SDCFH-12288-388 SDCFH-16384-388 Capacity1 32.1 MB 64.2 MB 128.4 MB 256.9 MB 512.5 MB 1024.9 MB 2048.9 MB 4097.8 MB 512.5 MB 1024.9 MB 2048.9 MB 4096.8 MB 4096 MB 8192 MB 12,288 MB 16,384 MB Capacity (formatted in bytes) 32,112,640 64,225,280 128,450,560 256,901,120 512,483,328 1,024,966,656 2,048,901,120 4,097,802,240 512,483,328 1,024,966,656 2,048,901,120 4,097,802,240 4,098,834,432 8,195,604,480 12,293,406,720 16,391,208,960 Sectors/Card (Max LBA+1) 62,720 125,440 250,880 501,760 1,000,944 2,001,888 4,001,760 8,003,520 1,000,944 2,001,888 4,001,760 8,003,521 8,005,536 16,007,040 24,010,560 32,014,080 No. of Heads 4 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 No. of Sectors/Track 32 32 32 32 63 63 63 63 63 63 63 63 63 63 63 63 No. of Cylinders 490 490 980 980 993 1,986 3,970 7,964 993 1,986 3,970 7,940 7,942 15,880 23,820 31,760
1 2
1 megabyte (MB)= 1 million bytes; 1 gigabyte (GB)= 1 billion bytes. Some of the listed capacity is used for formatting and other functions, and thus is not available for data storage. 4-GB with switch.
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Appendix B. Technical Support Services
Direct SanDisk Technical Support
Call SanDisk Applications Engineering at 408-542-0405 for technical support.
SanDisk Worldwide Web Site
Internet users can obtain technical support and product information along with SanDisk news and much more from the SanDisk Worldwide Web Site, 24 hours a day, seven days a week. The SanDisk Worldwide Web Site is frequently updated. Visit this site often to obtain the most up-to-date information on SanDisk products and applications. The SanDisk Web Site URL is http://www.sandisk.com.
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Technical Support Services
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Appendix C. SanDisk Worldwide Sales Offices
SanDisk Corporate Headquarters
140 Caspian Court Sunnyvale, CA 94089 Tel: 408-542-0500 Fax: 408-542-0503 http://www.sandisk.com
International OEM Sales
Europe SanDisk GmbH Karlsruher Str. 2C D-30519 Hannover, Germany Tel: 49-511-875-9131 Fax: 49-511-875-9187 Northern/Central/Southern Europe Rudolf-Diesel-Str. 3 40822 Mettmann, Germany Tel: 49-210-495-3433 Fax: 49-210-495-3434 Japan 8F Nisso Bldg. 15 2-17-19 Shin-Yokohama, Kohoku-ku Yokohama 222-0033, Japan Tel: 81-45-474-0181 Fax: 81-45-474-0371 Asia/Pacific Rim Suite 902-903 Bank of East Asia Harbour View Centre 56 Gloucester Road Wanchai, Hong Kong Tel: 852-2712-0501 Fax: 852-2712-9385
U.S. OEM Sales
Northwest/Southwest USA/ Mexico 140 Caspian Court Sunnyvale, CA 94089 Tel: 408-542-0730 Fax: 408-542-0410 North Central USA/South America 134 Cherry Creek Circle, Suite 150 Winter Srings, FL 32708 Tel: 407-366-6490 Fax: 407-366-5495 Northeastern USA/Canada 620 Herndon Pkwy. Suite 200 Herndon, VA 22070 Tel: 703-481-9828 Fax: 703-437-9215
To order SanDisk products directly from SanDisk, call 408-542-0595.
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SanDisk Worldwide Sales Offices
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Appendix D. Limited Warranty
I. WARRANTY STATEMENT
SanDisk warrants its products to be free of any defects in materials or workmanship that would prevent them from functioning properly for one year from the date of purchase. This express warranty is extended by SanDisk Corporation to its customers. II. GENERAL PROVISIONS This warranty sets forth the full extent of SanDisk's responsibilities regarding the SanDisk CompactFlash. In satisfaction of its obligations hereunder, SanDisk, at its sole option, will either repair, replace or refund the purchase price of the product. NOTWITHSTANDING ANYTHING ELSE IN THIS LIMITED WARRANTY OR OTHERWISE, THE EXPRESS WARRANTIES AND OBLIGATIONS OF SELLER AS SET FORTH IN THIS LIMITED WARRANTY, ARE IN LIEU OF, AND BUYER EXPRESSLY WAIVES ALL OTHER OBLIGATIONS, GUARANTIES AND WARRANTIES OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR INFRINGEMENT, TOGETHER WITH ANY LIABILITY OF SELLER UNDER ANY CONTRACT, NEGLIGENCE, STRICT LIABILITY OR OTHER LEGAL OR EQUITABLE THEORY FOR LOSS OF USE, REVENUE, OR PROFIT OR OTHER INCIDENTAL OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION PHYSICAL INJURY OR DEATH, PROPERTY DAMAGE, LOST DATA, OR COSTS OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES. IN NO EVENT SHALL THE SELLER BE LIABLE FOR DAMAGES IN EXCESS OF THE PURCHASE PRICE OF THE PRODUCT, ARISING OUT OF THE USE OR INABILITY TO USE SUCH PRODUCT, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. SanDisk's products are not warranted to operate without failure. III. WHAT THIS WARRANTY COVERS For products found to be defective within one year of purchase, SanDisk will have the option of repairing or replacing the defective product, if the following conditions are met:
A. B. C. The defective product is returned to SanDisk for failure analysis as soon as possible after the failure occurs. An incident card filled out by the user, explaining the conditions of usage and the nature of the failure, accompanies each returned defective product. No evidence is found of abuse or operation of products not in accordance with the published specifications, or of exceeding storage or maximum ratings or operating conditions.
All failing products returned to SanDisk under the provisions of this limited warranty shall be tested to the product's functional and performance specifications. Upon confirmation of failure, each product will be analyzed, by whatever means necessary, to determine the root cause of failure. If the root cause of failure is found to be not covered by the above provisions, then the product will be returned to the customer with a report indicating why the failure was not covered under the warranty.
This warranty does not cover defects, malfunctions, performance failures or damages to the unit resulting from use in other than its normal and customary manner, misuse, accident or neglect; or improper alterations or repairs. SanDisk reserves the right to repair or replace, at its discretion, any product returned by its customers, even if such product is not covered under warranty, but is under no obligation to do so.
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Limited Warranty
SanDisk may, at its discretion, ship repaired or rebuilt products identified in the same way as new products, provided such cards meet or exceed the same published specifications as new products. Concurrently, SanDisk also reserves the right to market any products, whether new, repaired, or rebuilt, under different specifications and product designations if such products do not meet the original product's specifications. IV. RECEIVING WARRANTY SERVICE According to SanDisk's warranty procedure, defective product should be returned only with prior authorization from SanDisk Corporation. Please contact SanDisk's Customer Service department at 408-542-0595 with the following information: product model number and description, nature of defect, conditions of use, proof of purchase and purchase date. If approved, SanDisk will issue a Return Material Authorization or Product Repair Authorization number. Ship the defective product to: SanDisk Corporation Attn: RMA Returns (Reference RMA or PRA #) 140 Caspian Court Sunnyvale, CA 94089 V. STATE LAW RIGHTS SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES, OR LIMITATION ON HOW LONG AN IMPLIED WARRANTY LASTS, SO THE ABOVE LIMITATIONS OR EXCLUSIONS MAY NOT APPLY TO YOU. This warranty gives you specific rights and you may also have other rights that vary from state to state.
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Appendix E. Disclaimer of Liability
SanDisk Corporation general policy does not recommend the use of its products in life support applications wherein a failure or malfunction of the product may directly threaten life or injury. Accordingly, in any use of products in life support systems or other applications where failure could cause damage, injury or loss of life, the products should only be incorporated in systems designed with appropriate redundancy, fault tolerant or back-up features. SanDisk shall not be liable for any loss, injury or damage caused by use of the Products in any of the following applications: - - - - special applications such as military related equipment, nuclear reactor control, and aerospace control devices for automotive vehicles, train, ship and traffic equipment safety system for disaster prevention and crime prevention medical-related equipment including medical measurement device
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